| /external/llvm/test/CodeGen/Mips/msa/ |
| D | spill.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
76 %r1 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
77 %r2 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r1, <16 x i8> %2)
78 %r3 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r2, <16 x i8> %3)
79 %r4 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r3, <16 x i8> %4)
80 %r5 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r4, <16 x i8> %5)
81 %r6 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r5, <16 x i8> %6)
82 %r7 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r6, <16 x i8> %7)
83 %r8 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r7, <16 x i8> %8)
84 %r9 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r8, <16 x i8> %9)
[all …]
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| D | elm_cxcmsa.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
9 %0 = tail call i32 @llvm.mips.cfcmsa(i32 0)
19 %0 = tail call i32 @llvm.mips.cfcmsa(i32 1)
29 %0 = tail call i32 @llvm.mips.cfcmsa(i32 2)
39 %0 = tail call i32 @llvm.mips.cfcmsa(i32 3)
49 %0 = tail call i32 @llvm.mips.cfcmsa(i32 4)
59 %0 = tail call i32 @llvm.mips.cfcmsa(i32 5)
69 %0 = tail call i32 @llvm.mips.cfcmsa(i32 6)
79 %0 = tail call i32 @llvm.mips.cfcmsa(i32 7)
89 tail call void @llvm.mips.ctcmsa(i32 0, i32 1)
[all …]
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| D | bit.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
12 %1 = tail call <16 x i8> @llvm.mips.sat.s.b(<16 x i8> %0, i32 7)
17 declare <16 x i8> @llvm.mips.sat.s.b(<16 x i8>, i32) nounwind
31 %1 = tail call <8 x i16> @llvm.mips.sat.s.h(<8 x i16> %0, i32 7)
36 declare <8 x i16> @llvm.mips.sat.s.h(<8 x i16>, i32) nounwind
50 %1 = tail call <4 x i32> @llvm.mips.sat.s.w(<4 x i32> %0, i32 7)
55 declare <4 x i32> @llvm.mips.sat.s.w(<4 x i32>, i32) nounwind
69 %1 = tail call <2 x i64> @llvm.mips.sat.s.d(<2 x i64> %0, i32 7)
74 declare <2 x i64> @llvm.mips.sat.s.d(<2 x i64>, i32) nounwind
88 %1 = tail call <16 x i8> @llvm.mips.sat.u.b(<16 x i8> %0, i32 7)
[all …]
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| D | i5-c.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
13 %1 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 14)
18 declare <16 x i8> @llvm.mips.ceqi.b(<16 x i8>, i32) nounwind
32 %1 = tail call <8 x i16> @llvm.mips.ceqi.h(<8 x i16> %0, i32 14)
37 declare <8 x i16> @llvm.mips.ceqi.h(<8 x i16>, i32) nounwind
51 %1 = tail call <4 x i32> @llvm.mips.ceqi.w(<4 x i32> %0, i32 14)
56 declare <4 x i32> @llvm.mips.ceqi.w(<4 x i32>, i32) nounwind
70 %1 = tail call <2 x i64> @llvm.mips.ceqi.d(<2 x i64> %0, i32 14)
75 declare <2 x i64> @llvm.mips.ceqi.d(<2 x i64>, i32) nounwind
89 %1 = tail call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %0, i32 14)
[all …]
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| D | i5-m.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
13 %1 = tail call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %0, i32 14)
18 declare <16 x i8> @llvm.mips.maxi.s.b(<16 x i8>, i32) nounwind
32 %1 = tail call <8 x i16> @llvm.mips.maxi.s.h(<8 x i16> %0, i32 14)
37 declare <8 x i16> @llvm.mips.maxi.s.h(<8 x i16>, i32) nounwind
51 %1 = tail call <4 x i32> @llvm.mips.maxi.s.w(<4 x i32> %0, i32 14)
56 declare <4 x i32> @llvm.mips.maxi.s.w(<4 x i32>, i32) nounwind
70 %1 = tail call <2 x i64> @llvm.mips.maxi.s.d(<2 x i64> %0, i32 14)
75 declare <2 x i64> @llvm.mips.maxi.s.d(<2 x i64>, i32) nounwind
89 %1 = tail call <16 x i8> @llvm.mips.maxi.u.b(<16 x i8> %0, i32 14)
[all …]
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| D | 3rf_int_float.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
15 %2 = tail call <4 x i32> @llvm.mips.fcaf.w(<4 x float> %0, <4 x float> %1)
20 declare <4 x i32> @llvm.mips.fcaf.w(<4 x float>, <4 x float>) nounwind
37 %2 = tail call <2 x i64> @llvm.mips.fcaf.d(<2 x double> %0, <2 x double> %1)
42 declare <2 x i64> @llvm.mips.fcaf.d(<2 x double>, <2 x double>) nounwind
59 %2 = tail call <4 x i32> @llvm.mips.fceq.w(<4 x float> %0, <4 x float> %1)
64 declare <4 x i32> @llvm.mips.fceq.w(<4 x float>, <4 x float>) nounwind
81 %2 = tail call <2 x i64> @llvm.mips.fceq.d(<2 x double> %0, <2 x double> %1)
86 declare <2 x i64> @llvm.mips.fceq.d(<2 x double>, <2 x double>) nounwind
103 %2 = tail call <4 x i32> @llvm.mips.fcle.w(<4 x float> %0, <4 x float> %1)
[all …]
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| D | i5_ld_st.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
13 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 16)
18 declare <16 x i8> @llvm.mips.ld.b(i8*, i32) nounwind
31 %1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 16)
36 declare <8 x i16> @llvm.mips.ld.h(i8*, i32) nounwind
49 %1 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 16)
54 declare <4 x i32> @llvm.mips.ld.w(i8*, i32) nounwind
67 %1 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 16)
72 declare <2 x i64> @llvm.mips.ld.d(i8*, i32) nounwind
86 tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 16)
[all …]
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| D | i5-b.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
13 %1 = tail call <16 x i8> @llvm.mips.bclri.b(<16 x i8> %0, i32 7)
18 declare <16 x i8> @llvm.mips.bclri.b(<16 x i8>, i32) nounwind
33 %1 = tail call <8 x i16> @llvm.mips.bclri.h(<8 x i16> %0, i32 7)
38 declare <8 x i16> @llvm.mips.bclri.h(<8 x i16>, i32) nounwind
52 %1 = tail call <4 x i32> @llvm.mips.bclri.w(<4 x i32> %0, i32 7)
57 declare <4 x i32> @llvm.mips.bclri.w(<4 x i32>, i32) nounwind
71 %1 = tail call <2 x i64> @llvm.mips.bclri.d(<2 x i64> %0, i32 7)
76 declare <2 x i64> @llvm.mips.bclri.d(<2 x i64>, i32) nounwind
92 %2 = tail call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %0, <16 x i8> %1, i32 7)
[all …]
|
| D | 3r-m.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
15 %2 = tail call <16 x i8> @llvm.mips.max.a.b(<16 x i8> %0, <16 x i8> %1)
20 declare <16 x i8> @llvm.mips.max.a.b(<16 x i8>, <16 x i8>) nounwind
37 %2 = tail call <8 x i16> @llvm.mips.max.a.h(<8 x i16> %0, <8 x i16> %1)
42 declare <8 x i16> @llvm.mips.max.a.h(<8 x i16>, <8 x i16>) nounwind
59 %2 = tail call <4 x i32> @llvm.mips.max.a.w(<4 x i32> %0, <4 x i32> %1)
64 declare <4 x i32> @llvm.mips.max.a.w(<4 x i32>, <4 x i32>) nounwind
81 %2 = tail call <2 x i64> @llvm.mips.max.a.d(<2 x i64> %0, <2 x i64> %1)
86 declare <2 x i64> @llvm.mips.max.a.d(<2 x i64>, <2 x i64>) nounwind
103 %2 = tail call <16 x i8> @llvm.mips.max.s.b(<16 x i8> %0, <16 x i8> %1)
[all …]
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| D | 3r-c.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
15 %2 = tail call <16 x i8> @llvm.mips.ceq.b(<16 x i8> %0, <16 x i8> %1)
20 declare <16 x i8> @llvm.mips.ceq.b(<16 x i8>, <16 x i8>) nounwind
37 %2 = tail call <8 x i16> @llvm.mips.ceq.h(<8 x i16> %0, <8 x i16> %1)
42 declare <8 x i16> @llvm.mips.ceq.h(<8 x i16>, <8 x i16>) nounwind
59 %2 = tail call <4 x i32> @llvm.mips.ceq.w(<4 x i32> %0, <4 x i32> %1)
64 declare <4 x i32> @llvm.mips.ceq.w(<4 x i32>, <4 x i32>) nounwind
81 %2 = tail call <2 x i64> @llvm.mips.ceq.d(<2 x i64> %0, <2 x i64> %1)
86 declare <2 x i64> @llvm.mips.ceq.d(<2 x i64>, <2 x i64>) nounwind
103 %2 = tail call <16 x i8> @llvm.mips.cle.s.b(<16 x i8> %0, <16 x i8> %1)
[all …]
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| D | 2r.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
12 %1 = tail call <16 x i8> @llvm.mips.nloc.b(<16 x i8> %0)
17 declare <16 x i8> @llvm.mips.nloc.b(<16 x i8>) nounwind
33 %1 = tail call <8 x i16> @llvm.mips.nloc.h(<8 x i16> %0)
38 declare <8 x i16> @llvm.mips.nloc.h(<8 x i16>) nounwind
54 %1 = tail call <4 x i32> @llvm.mips.nloc.w(<4 x i32> %0)
59 declare <4 x i32> @llvm.mips.nloc.w(<4 x i32>) nounwind
75 %1 = tail call <2 x i64> @llvm.mips.nloc.d(<2 x i64> %0)
80 declare <2 x i64> @llvm.mips.nloc.d(<2 x i64>) nounwind
96 %1 = tail call <16 x i8> @llvm.mips.nlzc.b(<16 x i8> %0)
[all …]
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| D | elm_shift_slide.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
15 %2 = tail call <16 x i8> @llvm.mips.sldi.b(<16 x i8> %0, <16 x i8> %1, i32 1)
20 declare <16 x i8> @llvm.mips.sldi.b(<16 x i8>, <16 x i8>, i32) nounwind
36 %2 = tail call <8 x i16> @llvm.mips.sldi.h(<8 x i16> %0, <8 x i16> %1, i32 1)
41 declare <8 x i16> @llvm.mips.sldi.h(<8 x i16>, <8 x i16>, i32) nounwind
57 %2 = tail call <4 x i32> @llvm.mips.sldi.w(<4 x i32> %0, <4 x i32> %1, i32 1)
62 declare <4 x i32> @llvm.mips.sldi.w(<4 x i32>, <4 x i32>, i32) nounwind
78 %2 = tail call <2 x i64> @llvm.mips.sldi.d(<2 x i64> %0, <2 x i64> %1, i32 1)
83 declare <2 x i64> @llvm.mips.sldi.d(<2 x i64>, <2 x i64>, i32) nounwind
97 %1 = tail call <16 x i8> @llvm.mips.splati.b(<16 x i8> %0, i32 1)
[all …]
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| D | 2rf_int_float.ll | 5 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
14 %1 = tail call <4 x i32> @llvm.mips.fclass.w(<4 x float> %0)
19 declare <4 x i32> @llvm.mips.fclass.w(<4 x float>) nounwind
35 %1 = tail call <2 x i64> @llvm.mips.fclass.d(<2 x double> %0)
40 declare <2 x i64> @llvm.mips.fclass.d(<2 x double>) nounwind
56 %1 = tail call <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float> %0)
61 declare <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float>) nounwind
77 %1 = tail call <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double> %0)
82 declare <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double>) nounwind
98 %1 = tail call <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float> %0)
[all …]
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| D | 3r-i.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
15 %2 = tail call <16 x i8> @llvm.mips.ilvev.b(<16 x i8> %0, <16 x i8> %1)
20 declare <16 x i8> @llvm.mips.ilvev.b(<16 x i8>, <16 x i8>) nounwind
37 %2 = tail call <8 x i16> @llvm.mips.ilvev.h(<8 x i16> %0, <8 x i16> %1)
42 declare <8 x i16> @llvm.mips.ilvev.h(<8 x i16>, <8 x i16>) nounwind
59 %2 = tail call <4 x i32> @llvm.mips.ilvev.w(<4 x i32> %0, <4 x i32> %1)
64 declare <4 x i32> @llvm.mips.ilvev.w(<4 x i32>, <4 x i32>) nounwind
81 %2 = tail call <2 x i64> @llvm.mips.ilvev.d(<2 x i64> %0, <2 x i64> %1)
86 declare <2 x i64> @llvm.mips.ilvev.d(<2 x i64>, <2 x i64>) nounwind
103 %2 = tail call <16 x i8> @llvm.mips.ilvl.b(<16 x i8> %0, <16 x i8> %1)
[all …]
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| D | 2rf_fq.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
13 %1 = tail call <4 x float> @llvm.mips.ffql.w(<8 x i16> %0)
18 declare <4 x float> @llvm.mips.ffql.w(<8 x i16>) nounwind
32 %1 = tail call <2 x double> @llvm.mips.ffql.d(<4 x i32> %0)
37 declare <2 x double> @llvm.mips.ffql.d(<4 x i32>) nounwind
51 %1 = tail call <4 x float> @llvm.mips.ffqr.w(<8 x i16> %0)
56 declare <4 x float> @llvm.mips.ffqr.w(<8 x i16>) nounwind
70 %1 = tail call <2 x double> @llvm.mips.ffqr.d(<4 x i32> %0)
75 declare <2 x double> @llvm.mips.ffqr.d(<4 x i32>) nounwind
|
| D | i10.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
11 %1 = tail call i32 @llvm.mips.bnz.b(<16 x i8> %0)
20 declare i32 @llvm.mips.bnz.b(<16 x i8>) nounwind
32 %1 = tail call i32 @llvm.mips.bnz.h(<8 x i16> %0)
41 declare i32 @llvm.mips.bnz.h(<8 x i16>) nounwind
53 %1 = tail call i32 @llvm.mips.bnz.w(<4 x i32> %0)
62 declare i32 @llvm.mips.bnz.w(<4 x i32>) nounwind
74 %1 = tail call i32 @llvm.mips.bnz.d(<2 x i64> %0)
83 declare i32 @llvm.mips.bnz.d(<2 x i64>) nounwind
|
| D | i8.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
12 %1 = tail call <16 x i8> @llvm.mips.andi.b(<16 x i8> %0, i32 25)
17 declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32) nounwind
33 %2 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 25)
38 declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, <16 x i8>, i32) nounwind
57 %2 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 25)
62 declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, <16 x i8>, i32) nounwind
82 %2 = tail call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %0, <16 x i8> %1, i32 25)
87 declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, <16 x i8>, i32) nounwind
104 %1 = tail call <16 x i8> @llvm.mips.nori.b(<16 x i8> %0, i32 25)
[all …]
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| /external/llvm/test/CodeGen/Mips/ |
| D | dsp-r1.ll | 7 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)
11 declare i32 @llvm.mips.extr.w(i64, i32) nounwind
17 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1)
25 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15)
29 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
35 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1)
39 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
45 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15)
49 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
55 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 %a1)
[all …]
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| D | dsp-r2.ll | 9 %3 = tail call i64 @llvm.mips.dpa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
13 declare i64 @llvm.mips.dpa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone
21 %3 = tail call i64 @llvm.mips.dps.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
25 declare i64 @llvm.mips.dps.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone
33 %3 = tail call i64 @llvm.mips.mulsa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
37 declare i64 @llvm.mips.mulsa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone
45 %3 = tail call i64 @llvm.mips.dpax.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
49 declare i64 @llvm.mips.dpax.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone
57 %3 = tail call i64 @llvm.mips.dpsx.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
61 declare i64 @llvm.mips.dpsx.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone
[all …]
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| D | adjust-callstack-sp.ll | 1 ; RUN: llc < %s -march=mips -mcpu=mips16 | FileCheck %s -check-prefix=M16
2 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=GP32
3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=GP32
4 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32
5 ; RUN: llc < %s -march=mips -mcpu=mips3 | FileCheck %s -check-prefix=GP64
6 ; RUN: llc < %s -march=mips -mcpu=mips64 | FileCheck %s -check-prefix=GP64
7 ; RUN: llc < %s -march=mips -mcpu=mips64r6 | FileCheck %s -check-prefix=GP64
|
| /external/libvpx/libvpx/vp9/ |
| D | vp9_common.mk | 94 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_common_dspr2.h
95 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_avg_dspr2.c
96 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_avg_horiz_dspr2.c
97 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_dspr2.c
98 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_horiz_dspr2.c
99 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_vert_dspr2.c
100 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_avg_dspr2.c
101 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_avg_horiz_dspr2.c
102 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_dspr2.c
103 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_horiz_dspr2.c
[all …]
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| /external/v8/ |
| D | Android.v8common.mk | 274 src/ic/mips/access-compiler-mips.cc\
275 src/ic/mips/handler-compiler-mips.cc \
276 src/ic/mips/ic-compiler-mips.cc \
277 src/ic/mips/ic-mips.cc \
278 src/ic/mips/stub-cache-mips.cc \
279 src/mips/assembler-mips.cc \
280 src/mips/builtins-mips.cc \
281 src/mips/code-stubs-mips.cc \
282 src/mips/codegen-mips.cc \
283 src/mips/constants-mips.cc \
[all …]
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| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | call.ll | 3 ; FIXME: We should remove the need for -enable-mips-tail-calls
4 ; RUN: llc -march=mips -mcpu=mips32 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=A…
5 ; RUN: llc -march=mips -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=A…
6 ; RUN: llc -march=mips -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=A…
7 ; RUN: llc -march=mips -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=A…
8 ; RUN: llc -march=mips -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=A…
9 ; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=A…
10 ; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=A…
11 ; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=A…
12 ; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=A…
[all …]
|
| /external/libvpx/mips-dspr2/ |
| D | libvpx_srcs.txt | 35 vp8/common/mips/dspr2/dequantize_dspr2.c
36 vp8/common/mips/dspr2/filter_dspr2.c
37 vp8/common/mips/dspr2/idct_blk_dspr2.c
38 vp8/common/mips/dspr2/idctllm_dspr2.c
39 vp8/common/mips/dspr2/loopfilter_filters_dspr2.c
40 vp8/common/mips/dspr2/reconinter_dspr2.c
131 vp9/common/mips/dspr2/vp9_common_dspr2.h
132 vp9/common/mips/dspr2/vp9_convolve2_avg_dspr2.c
133 vp9/common/mips/dspr2/vp9_convolve2_avg_horiz_dspr2.c
134 vp9/common/mips/dspr2/vp9_convolve2_dspr2.c
[all …]
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| /external/v8/test/cctest/ |
| D | OWNERS | 1 per-file *-mips*=paul.lind@imgtec.com
2 per-file *-mips*=gergely.kis@imgtec.com
3 per-file *-mips*=akos.palfi@imgtec.com
4 per-file *-mips*=balazs.kilvady@imgtec.com
5 per-file *-mips*=dusan.milosavljevic@imgtec.com
|