| /external/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 166 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
169 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
177 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
180 !strconcat(opstr, "\t$rt, $addr"),
187 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
190 !strconcat(opstr, "\t$rt, $addr"),
210 class MovePMM16<string opstr, RegisterOperand RO> :
212 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
231 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
234 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
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| D | MipsInstrInfo.td | 586 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
590 !strconcat(opstr, "\t$rd, $rs, $rt"),
591 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
598 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
603 !strconcat(opstr, "\t$rt, $rs, $imm16"),
605 Itin, FrmI, opstr> {
611 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
613 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
620 class LogicNOR<string opstr, RegisterOperand RO>:
622 !strconcat(opstr, "\t$rd, $rs, $rt"),
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| D | MipsInstrFPU.td | 102 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
105 !strconcat(opstr, "\t$fd, $fs, $ft"),
106 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> {
110 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
112 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
114 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin,
121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
127 multiclass ABSS_M<string opstr, InstrItinClass Itin,
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| D | MipsCondMov.td | 19 class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
22 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {
27 class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
30 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr> {
35 class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
38 !strconcat(opstr, "\t$rd, $rs, $fcc"),
40 Itin, FrmFR, opstr> {
45 class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
48 !strconcat(opstr, "\t$fd, $fs, $fcc"),
50 Itin, FrmFR, opstr> {
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| D | Mips64InstrInfo.td | 312 class Count1s<string opstr, RegisterOperand RO>:
313 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
314 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
318 class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
320 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
322 NoItinerary, FrmR, opstr> {
326 class SetCC64_R<string opstr, PatFrag cond_op> :
328 !strconcat(opstr, "\t$rd, $rs, $rt"),
331 II_SEQ_SNE, FrmR, opstr> {
335 class SetCC64_I<string opstr, PatFrag cond_op>:
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| D | MipsInstrFormats.td | 95 InstrItinClass itin, Format f, string opstr = ""> :
98 string BaseOpcode = opstr;
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| D | Mips32r6InstrInfo.td | 375 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
378 string AsmString = !strconcat(opstr, "\t$rt, $offset");
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| /external/icu/icu4c/source/test/cintltst/ |
| D | putiltst.c | 314 const char *opstr; in TestCompareVersions() local
322 opstr = testCases[j+1]; in TestCompareVersions()
324 switch(opstr[0]) { in TestCompareVersions()
339 log_verbose("%d: %s %s %s, OK\n", (j/3), v1str, opstr, v2str); in TestCompareVersions()
341 …log_err("%d: %s %s %s: wanted values of the same sign, %d got %d\n", (j/3), v1str, opstr, v2str, o… in TestCompareVersions()
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| /external/regex-re2/re2/ |
| D | parse.cc | 2065 StringPiece opstr = t; in Parse()
2083 opstr.set(opstr.data(), t.data() - opstr.data()); in Parse()
2084 if (!ps.PushRepeatOp(op, opstr, nongreedy)) in Parse()
2086 isunary = opstr; in Parse()
2092 StringPiece opstr = t; in Parse() local
2114 opstr.set(opstr.data(), t.data() - opstr.data()); in Parse()
2115 if (!ps.PushRepetition(lo, hi, opstr, nongreedy)) in Parse()
2117 isunary = opstr; in Parse()
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| /external/google-breakpad/src/third_party/libdisasm/ |
| D | x86_format.c | 1090 struct op_string * opstr = (struct op_string *) arg; in format_op_raw() local
1092 format_operand_raw(op, insn, opstr->buf, opstr->len); in format_op_raw()
1114 struct op_string opstr = { buf, len }; in format_raw_insn() local
1158 opstr.len = len; in format_raw_insn()
1159 x86_operand_foreach( insn, format_op_raw, &opstr, op_any ); in format_raw_insn()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 1084 class LoadParamScalar4Inst<NVPTXRegClass regclass, string opstr> :
1087 !strconcat(!strconcat("ld.param", opstr),
1090 class LoadParamScalar2Inst<NVPTXRegClass regclass, string opstr> :
1093 !strconcat(!strconcat("ld.param", opstr),
1097 class StoreParamScalar4Inst<NVPTXRegClass regclass, string opstr> :
1101 !strconcat(!strconcat("st.param", opstr),
1104 class StoreParamScalar2Inst<NVPTXRegClass regclass, string opstr> :
1107 !strconcat(!strconcat("st.param", opstr),
1110 class StoreRetvalScalar4Inst<NVPTXRegClass regclass, string opstr> :
1114 !strconcat(!strconcat("st.param", opstr),
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| D | NVPTXInstrInfo.td | 1765 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1767 !strconcat(!strconcat("ld.param", opstr),
1771 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
1773 !strconcat(!strconcat("mov", opstr),
1777 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1779 !strconcat(!strconcat("ld.param.v2", opstr),
1782 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1786 !strconcat(!strconcat("ld.param.v4", opstr),
1789 class StoreParamInst<NVPTXRegClass regclass, string opstr> :
1791 !strconcat(!strconcat("st.param", opstr),
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