Home
last modified time | relevance | path

Searched refs:reg1 (Results 1 – 25 of 72) sorted by relevance

123

/external/libavc/common/armv8/
Dih264_neon_macros.s36 .macro swp reg1, reg2
37 eor \reg1, \reg1, \reg2
38 eor \reg2, \reg1, \reg2
39 eor \reg1, \reg1, \reg2
/external/libmpeg2/common/armv8/
Dimpeg2_neon_macros.s53 .macro swp reg1, reg2
54 eor \reg1, \reg1, \reg2
55 eor \reg2, \reg1, \reg2
56 eor \reg1, \reg1, \reg2
/external/llvm/test/CodeGen/R600/
Dmax-literals.ll6 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
11 %3 = extractelement <4 x float> %reg1, i32 3
35 define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
37 %0 = extractelement <4 x float> %reg1, i32 0
38 %1 = extractelement <4 x float> %reg1, i32 1
39 %2 = extractelement <4 x float> %reg1, i32 2
40 %3 = extractelement <4 x float> %reg1, i32 3
Drv7x0_count3.ll5 define void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
6 %1 = extractelement <4 x float> %reg1, i32 0
7 %2 = extractelement <4 x float> %reg1, i32 1
8 %3 = extractelement <4 x float> %reg1, i32 2
9 %4 = extractelement <4 x float> %reg1, i32 3
Dswizzle-export.ll9 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
11 %0 = extractelement <4 x float> %reg1, i32 0
12 %1 = extractelement <4 x float> %reg1, i32 1
13 %2 = extractelement <4 x float> %reg1, i32 2
14 %3 = extractelement <4 x float> %reg1, i32 3
99 define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
101 %0 = extractelement <4 x float> %reg1, i32 0
102 %1 = extractelement <4 x float> %reg1, i32 1
Dpv-packing.ll6 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x f…
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
Dschedule-fs-loop-nested-if.ll4 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #1 {
6 %0 = extractelement <4 x float> %reg1, i32 0
7 %1 = extractelement <4 x float> %reg1, i32 1
8 %2 = extractelement <4 x float> %reg1, i32 2
9 %3 = extractelement <4 x float> %reg1, i32 3
Dr600cfg.ll3 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
5 %0 = extractelement <4 x float> %reg1, i32 0
6 %1 = extractelement <4 x float> %reg1, i32 1
7 %2 = extractelement <4 x float> %reg1, i32 2
8 %3 = extractelement <4 x float> %reg1, i32 3
Dload-input-fold.ll3 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x f…
5 %0 = extractelement <4 x float> %reg1, i32 0
6 %1 = extractelement <4 x float> %reg1, i32 1
7 %2 = extractelement <4 x float> %reg1, i32 2
8 %3 = extractelement <4 x float> %reg1, i32 3
Dschedule-vs-if-nested-loop.ll4 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
6 %0 = extractelement <4 x float> %reg1, i32 0
7 %1 = extractelement <4 x float> %reg1, i32 1
8 %2 = extractelement <4 x float> %reg1, i32 2
9 %3 = extractelement <4 x float> %reg1, i32 3
Dshared-op-cycle.ll7 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
9 %w1 = extractelement <4 x float> %reg1, i32 3
Dschedule-vs-if-nested-loop-failure.ll10 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
12 %0 = extractelement <4 x float> %reg1, i32 0
13 %1 = extractelement <4 x float> %reg1, i32 2
40 %15 = extractelement <4 x float> %reg1, i32 1
41 %16 = extractelement <4 x float> %reg1, i32 3
Dr600-export-fix.ll13 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
15 %0 = extractelement <4 x float> %reg1, i32 0
16 %1 = extractelement <4 x float> %reg1, i32 1
17 %2 = extractelement <4 x float> %reg1, i32 2
18 %3 = extractelement <4 x float> %reg1, i32 3
Dllvm.pow.ll30 define void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
31 %vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1)
Dpv.ll6 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x f…
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
11 %3 = extractelement <4 x float> %reg1, i32 3
/external/boringssl/src/crypto/perlasm/
Dx86gas.pl70 { my($addr,$reg1,$reg2,$idx)=@_;
73 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
79 $reg1 = "%$reg1" if ($reg1);
86 $ret .= "($reg1,$reg2,$idx)";
88 elsif ($reg1)
89 { $ret .= "($reg1)"; }
Dx86nasm.pl36 { my($size,$addr,$reg1,$reg2,$idx)=@_;
39 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
62 $ret .= "+$reg1" if ($reg1 ne "");
65 { $ret .= "$reg1"; }
Dx86masm.pl39 { my($size,$addr,$reg1,$reg2,$idx)=@_;
42 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
61 $ret .= "+$reg1" if ($reg1 ne "");
64 { $ret .= "$reg1"; }
/external/mesa3d/src/mesa/program/
Dregister_allocate.c189 struct ra_reg *reg1 = &regs->regs[r1]; in ra_add_conflict_list() local
191 if (reg1->conflict_list_size == reg1->num_conflicts) { in ra_add_conflict_list()
192 reg1->conflict_list_size *= 2; in ra_add_conflict_list()
193 reg1->conflict_list = reralloc(regs->regs, reg1->conflict_list, in ra_add_conflict_list()
194 unsigned int, reg1->conflict_list_size); in ra_add_conflict_list()
196 reg1->conflict_list[reg1->num_conflicts++] = r2; in ra_add_conflict_list()
197 reg1->conflicts[r2] = GL_TRUE; in ra_add_conflict_list()
/external/llvm/test/CodeGen/ARM/
Dfast-isel-pic.ll17 ; THUMB-ELF: ldr r[[reg1:[0-9]+]],
18 ; THUMB-ELF: ldr r[[reg0]], [r[[reg0]], r[[reg1]]]
20 ; ARM: ldr [[reg1:r[0-9]+]],
21 ; ARM: add [[reg1]], pc, [[reg1]]
/external/libunwind/src/ptrace/
D_UPT_access_mem.c63 long reg1, reg2; in _UPT_access_mem()
64 reg1 = ptrace (PTRACE_PEEKDATA, pid, (void*) (uintptr_t) addr, 0); in _UPT_access_mem()
70 *val = ((unw_word_t)(reg2) << 32) | (uint32_t) reg1; in _UPT_access_mem()
/external/aac/libFDK/src/
Dfixpoint_math.cpp430 FIXP_DBL reg1, reg2, regtmp ; in invSqrtNorm2() local
445 reg1 = invSqrtTab[ (INT)(val>>(DFRACT_BITS-1-(SQRT_BITS+1))) & SQRT_BITS_MASK ]; in invSqrtNorm2()
448 regtmp= fPow2Div2(reg1); /* a = Q^2 */ in invSqrtNorm2()
450 reg1 += (fMultDiv2(regtmp, reg1)<<4); /* Q = Q + Q*b */ in invSqrtNorm2()
455 reg1 = fMultDiv2(reg1, reg2) << 2; in invSqrtNorm2()
460 return(reg1); in invSqrtNorm2()
/external/llvm/test/CodeGen/X86/
Davoid_complex_am.ll4 ; On X86, reg1 + 1*reg2 has the same cost as reg1 + 8*reg2.
/external/llvm/test/MC/MachO/
Dbad-macro.s5 .macro test_macro reg1, reg2
/external/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp150 bool haveSameParity(unsigned reg1, unsigned reg2) { in haveSameParity() argument
151 assert(isFPReg(reg1) && "Expecting an FP register for reg1"); in haveSameParity()
154 return isOdd(reg1) == isOdd(reg2); in haveSameParity()

123