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Searched refs:reg3 (Results 1 – 25 of 35) sorted by relevance

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/external/llvm/test/CodeGen/ARM/
Dfast-isel-pic.ll30 ; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
31 ; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
41 ; THUMB: movw r[[reg3:[0-9]+]],
42 ; THUMB: movt r[[reg3]],
43 ; THUMB: add r[[reg3]], pc
44 ; THUMB: ldr r[[reg3]], [r[[reg3]]]
46 ; THUMB-ELF: ldr r[[reg3:[0-9]+]],
48 ; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]]
/external/llvm/test/CodeGen/R600/
Dpv-packing.ll6 …float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 {
14 %6 = extractelement <4 x float> %reg3, i32 0
15 %7 = extractelement <4 x float> %reg3, i32 1
16 %8 = extractelement <4 x float> %reg3, i32 2
Dload-input-fold.ll3 …float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 {
13 %8 = extractelement <4 x float> %reg3, i32 0
14 %9 = extractelement <4 x float> %reg3, i32 1
15 %10 = extractelement <4 x float> %reg3, i32 2
16 %11 = extractelement <4 x float> %reg3, i32 3
Dpv.ll6 …eg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg …
16 %8 = extractelement <4 x float> %reg3, i32 0
17 %9 = extractelement <4 x float> %reg3, i32 1
18 %10 = extractelement <4 x float> %reg3, i32 2
19 %11 = extractelement <4 x float> %reg3, i32 3
Dbig_alu.ll6 …eg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg …
34 %26 = extractelement <4 x float> %reg3, i32 0
35 %27 = extractelement <4 x float> %reg3, i32 1
36 %28 = extractelement <4 x float> %reg3, i32 2
37 %29 = extractelement <4 x float> %reg3, i32 3
/external/valgrind/none/tests/s390x/
Dcksm.c27 register uint64_t reg3 asm("3") = len; in cksm_by_insn()
33 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory"); in cksm_by_insn()
36 len = reg3; in cksm_by_insn()
/external/elfutils/src/tests/
Drun-varlocs.sh68 [40051c,40052a) {reg3}
107 [400408,400421) {reg3}
Drun-addrcfi.sh35 integer reg3 (%ebx): same_value
82 integer reg3 (%ebx): same_value
134 integer reg3 (%rbx): undefined
200 integer reg3 (%rbx): undefined
304 integer reg3 (r3): undefined
1331 integer reg3 (r3): undefined
2357 integer reg3 (%r3): undefined
2434 integer reg3 (%r3): undefined
2512 integer reg3 (r3): undefined
2588 integer reg3 (x3): undefined
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.cc2438 const Register& reg3, in Include() argument
2441 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Include()
2451 const FPRegister& reg3, in Include() argument
2453 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Include()
2470 const Register& reg3, in Exclude() argument
2472 RegList exclude = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Exclude()
2479 const FPRegister& reg3, in Exclude() argument
2481 RegList excludefp = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Exclude()
2488 const CPURegister& reg3, in Exclude() argument
2493 const CPURegister regs[] = {reg1, reg2, reg3, reg4}; in Exclude()
Dassembler-a64.h409 const CPURegister& reg3 = NoReg,
423 const CPURegister& reg3 = NoCPUReg,
436 const VRegister& reg3 = NoVReg,
446 const VRegister& reg3 = NoVReg,
455 CPURegister reg3 = NoCPUReg,
457 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
459 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
Dassembler-a64.cc5363 const CPURegister& reg3, const CPURegister& reg4, in AreAliased() argument
5372 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
5398 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType() argument
5404 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1); in AreSameSizeAndType()
5415 const VRegister& reg3, const VRegister& reg4) { in AreSameFormat() argument
5419 match &= !reg3.IsValid() || reg3.IsSameFormat(reg1); in AreSameFormat()
5426 const VRegister& reg3, const VRegister& reg4) { in AreConsecutive() argument
5431 match &= !reg3.IsValid() || in AreConsecutive()
5432 (reg3.code() == ((reg1.code() + 2) % kNumberOfVRegisters)); in AreConsecutive()
Dmacro-assembler-a64.h3219 const Register& reg3 = NoReg,
3223 const VRegister& reg3 = NoVReg,
3233 const Register& reg3 = NoReg,
3237 const VRegister& reg3 = NoVReg,
3241 const CPURegister& reg3 = NoCPUReg,
/external/skia/gm/
Dglyph_pos.cpp191 static GMRegistry reg3(GlyphPosHairlineStrokeFactory);
Dbitmaprect.cpp294 static skiagm::GMRegistry reg3(MyFactory3);
Dgradients_2pt_conical.cpp373 static GMRegistry reg3(MyFactory3);
/external/v8/src/arm64/
Dassembler-arm64.h412 Register reg3 = NoReg,
420 const CPURegister& reg3 = NoReg,
433 const CPURegister& reg3 = NoCPUReg,
450 CPURegister reg3 = NoCPUReg,
452 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
454 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
Dassembler-arm64.cc207 Register reg3, Register reg4) { in GetAllocatableRegisterThatIsNotOneOf() argument
208 CPURegList regs(reg1, reg2, reg3, reg4); in GetAllocatableRegisterThatIsNotOneOf()
220 const CPURegister& reg3, const CPURegister& reg4, in AreAliased() argument
229 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
257 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType() argument
263 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1); in AreSameSizeAndType()
/external/v8/src/arm/
Dmacro-assembler-arm.cc3947 Register reg3, in GetRegisterThatIsNotOneOf() argument
3954 if (reg3.is_valid()) regs |= reg3.bit(); in GetRegisterThatIsNotOneOf()
3998 Register reg3, in AreAliased() argument
4005 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
4011 if (reg3.is_valid()) regs |= reg3.bit(); in AreAliased()
Dmacro-assembler-arm.h50 Register reg3 = no_reg,
59 Register reg3 = no_reg,
/external/libvpx/libvpx/vp9/common/arm/neon/
Dvp9_idct32x32_add_neon.asm241 …DO_BUTTERFLY $regC, $regD, $regA, $regB, $first_constant, $second_constant, $reg1, $reg2, $reg3, $…
278 vqrshrn.s32 $reg3, q11, #14
286 DO_BUTTERFLY_STD $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
287 DO_BUTTERFLY d28, d29, d26, d27, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
/external/llvm/include/llvm/Support/
DDwarf.def198 HANDLE_DW_OP(0x53, reg3)
/external/v8/src/mips/
Dmacro-assembler-mips.h82 Register reg3 = no_reg,
89 Register reg3 = no_reg,
/external/v8/src/mips64/
Dmacro-assembler-mips64.h88 Register reg3 = no_reg,
95 Register reg3 = no_reg,
Dmacro-assembler-mips64.cc5934 Register reg3, in GetRegisterThatIsNotOneOf() argument
5941 if (reg3.is_valid()) regs |= reg3.bit(); in GetRegisterThatIsNotOneOf()
5982 Register reg3, in AreAliased() argument
5989 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
5995 if (reg3.is_valid()) regs |= reg3.bit(); in AreAliased()
/external/v8/src/x87/
Dmacro-assembler-x87.cc2972 Register reg3, in AreAliased() argument
2979 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
2985 if (reg3.is_valid()) regs |= reg3.bit(); in AreAliased()

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