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Searched refs:reg5 (Results 1 – 25 of 27) sorted by relevance

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/external/elfutils/src/tests/
Drun-varlocs.sh57 [400500,400504) {reg5}
63 [400510,40051c) {reg5}
65 [40052b,400531) {GNU_entry_value(1) {reg5}, stack_value}
78 [400400,400406) {reg5}
80 [40040a,40040b) {GNU_entry_value(1) {reg5}, stack_value}
92 [400510,400523) {reg5}
106 [400400,400408) {reg5}
108 [400421,400423) {GNU_entry_value(1) {reg5}, stack_value}
120 [400500,400503) {reg5}
122 [400500,400503) {GNU_implicit_pointer([4a],0) {reg5}}
Drun-readelf-loc.sh66 [ 0] 0x0000000000400480 <main>..0x000000000040048d <main+0xd> [ 0] reg5
67 [ 23] 0x0000000000400485 <main+0x5>..0x000000000040048d <main+0xd> [ 0] reg5
82 [ 0] 0x0000000000400480..0x000000000040048d [ 0] reg5
83 [ 23] 0x0000000000400485..0x000000000040048d [ 0] reg5
98 [ 0] 000000000000000000..0x000000000000000d [ 0] reg5
99 [ 23] 0x0000000000000005..0x000000000000000d [ 0] reg5
Drun-readelf-zdebug.sh49 [ 0] 0x00000000004003c0..0x00000000004003c3 [ 0] reg5
53 [ 0] reg5
Drun-addrcfi.sh37 integer reg5 (%ebp): same_value
84 integer reg5 (%ebp): same_value
136 integer reg5 (%rdi): undefined
202 integer reg5 (%rdi): undefined
306 integer reg5 (r5): undefined
1333 integer reg5 (r5): undefined
2359 integer reg5 (%r5): undefined
2436 integer reg5 (%r5): undefined
2514 integer reg5 (r5): same_value
2590 integer reg5 (x5): undefined
/external/llvm/test/CodeGen/ARM/
Dfast-isel-pic.ll53 ; ARMv7: movw r[[reg5:[0-9]+]],
54 ; ARMv7: movt r[[reg5]],
55 ; ARMv7: add r[[reg5]], pc, r[[reg5]]
56 ; ARMv7: ldr r[[reg5]], [r[[reg5]]]
58 ; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
60 ; ARMv7-ELF-NEXT: add r[[reg5]], pc
62 ; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
/external/llvm/test/DebugInfo/
Ddwarfdump-debug-frame-simple.test22 ; FRAMES-NEXT: DW_CFA_offset: reg5 -8
24 ; FRAMES-NEXT: DW_CFA_def_cfa_register: reg5
/external/llvm/test/CodeGen/R600/
Dpv.ll6 …eg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg …
24 %16 = extractelement <4 x float> %reg5, i32 0
25 %17 = extractelement <4 x float> %reg5, i32 1
26 %18 = extractelement <4 x float> %reg5, i32 2
27 %19 = extractelement <4 x float> %reg5, i32 3
Dbig_alu.ll6 …eg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg …
42 %34 = extractelement <4 x float> %reg5, i32 0
43 %35 = extractelement <4 x float> %reg5, i32 1
44 %36 = extractelement <4 x float> %reg5, i32 2
45 %37 = extractelement <4 x float> %reg5, i32 3
/external/skia/gm/
Dglyph_pos.cpp193 static GMRegistry reg5(GlyphPosHairlineFillFactory);
/external/v8/src/arm64/
Dassembler-arm64.cc221 const CPURegister& reg5, const CPURegister& reg6, in AreAliased() argument
229 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
258 const CPURegister& reg5, const CPURegister& reg6, in AreSameSizeAndType() argument
265 match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1); in AreSameSizeAndType()
Dassembler-arm64.h422 const CPURegister& reg5 = NoReg,
435 const CPURegister& reg5 = NoCPUReg,
/external/v8/src/arm/
Dmacro-assembler-arm.cc3949 Register reg5, in GetRegisterThatIsNotOneOf() argument
3956 if (reg5.is_valid()) regs |= reg5.bit(); in GetRegisterThatIsNotOneOf()
4000 Register reg5, in AreAliased() argument
4005 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
4013 if (reg5.is_valid()) regs |= reg5.bit(); in AreAliased()
Dmacro-assembler-arm.h52 Register reg5 = no_reg,
61 Register reg5 = no_reg,
/external/llvm/include/llvm/Support/
DDwarf.def200 HANDLE_DW_OP(0x55, reg5)
/external/v8/src/mips/
Dmacro-assembler-mips.h84 Register reg5 = no_reg,
91 Register reg5 = no_reg,
Dmacro-assembler-mips.cc5951 Register reg5, in GetRegisterThatIsNotOneOf() argument
5958 if (reg5.is_valid()) regs |= reg5.bit(); in GetRegisterThatIsNotOneOf()
5999 Register reg5, in AreAliased() argument
6004 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
6012 if (reg5.is_valid()) regs |= reg5.bit(); in AreAliased()
/external/v8/src/mips64/
Dmacro-assembler-mips64.h90 Register reg5 = no_reg,
97 Register reg5 = no_reg,
Dmacro-assembler-mips64.cc5936 Register reg5, in GetRegisterThatIsNotOneOf() argument
5943 if (reg5.is_valid()) regs |= reg5.bit(); in GetRegisterThatIsNotOneOf()
5984 Register reg5, in AreAliased() argument
5989 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
5997 if (reg5.is_valid()) regs |= reg5.bit(); in AreAliased()
/external/v8/src/x87/
Dmacro-assembler-x87.cc2974 Register reg5, in AreAliased() argument
2979 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
2987 if (reg5.is_valid()) regs |= reg5.bit(); in AreAliased()
Dmacro-assembler-x87.h39 Register reg5 = no_reg,
/external/v8/src/ia32/
Dmacro-assembler-ia32.cc3014 Register reg5, in AreAliased() argument
3019 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
3027 if (reg5.is_valid()) regs |= reg5.bit(); in AreAliased()
Dmacro-assembler-ia32.h39 Register reg5 = no_reg,
/external/elfutils/src/libdw/
Dknown-dwarf.h522 ONE_KNOWN_DW_OP_DESC (reg5, DW_OP_reg5, "Register 5.") \
/external/vixl/src/vixl/a64/
Dassembler-a64.cc5364 const CPURegister& reg5, const CPURegister& reg6, in AreAliased() argument
5372 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
5399 const CPURegister& reg5, const CPURegister& reg6, in AreSameSizeAndType() argument
5406 match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1); in AreSameSizeAndType()
/external/v8/src/x64/
Dmacro-assembler-x64.h59 Register reg5 = no_reg,

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