| /external/llvm/test/CodeGen/R600/ |
| D | pv.ll | 6 …float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7) #0 {
32 %24 = extractelement <4 x float> %reg7, i32 0
33 %25 = extractelement <4 x float> %reg7, i32 1
34 %26 = extractelement <4 x float> %reg7, i32 2
35 %27 = extractelement <4 x float> %reg7, i32 3
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| D | big_alu.ll | 6 …eg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg …
50 %42 = extractelement <4 x float> %reg7, i32 0
51 %43 = extractelement <4 x float> %reg7, i32 1
52 %44 = extractelement <4 x float> %reg7, i32 2
53 %45 = extractelement <4 x float> %reg7, i32 3
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| /external/elfutils/src/tests/ |
| D | run-addrcfi.sh | 39 integer reg7 (%edi): same_value
86 integer reg7 (%edi): same_value
138 integer reg7 (%rsp): location expression: call_frame_cfa stack_value
204 integer reg7 (%rsp): location expression: call_frame_cfa stack_value
308 integer reg7 (r7): undefined
1335 integer reg7 (r7): undefined
2361 integer reg7 (%r7): same_value
2438 integer reg7 (%r7): same_value
2516 integer reg7 (r7): same_value
2592 integer reg7 (x7): undefined
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 222 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased() argument
229 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
259 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType() argument
267 match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1); in AreSameSizeAndType()
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| D | assembler-arm64.h | 424 const CPURegister& reg7 = NoReg,
437 const CPURegister& reg7 = NoCPUReg,
|
| /external/llvm/include/llvm/Support/ |
| D | Dwarf.def | 202 HANDLE_DW_OP(0x57, reg7)
|
| /external/v8/src/x87/ |
| D | macro-assembler-x87.cc | 2976 Register reg7, in AreAliased() argument
2980 reg7.is_valid() + reg8.is_valid(); in AreAliased()
2989 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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| D | macro-assembler-x87.h | 41 Register reg7 = no_reg,
|
| /external/v8/src/ia32/ |
| D | macro-assembler-ia32.cc | 3016 Register reg7, in AreAliased() argument
3020 reg7.is_valid() + reg8.is_valid(); in AreAliased()
3029 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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| D | macro-assembler-ia32.h | 41 Register reg7 = no_reg,
|
| /external/elfutils/src/libdw/ |
| D | known-dwarf.h | 524 ONE_KNOWN_DW_OP_DESC (reg7, DW_OP_reg7, "Register 7.") \
|
| /external/v8/src/arm/ |
| D | macro-assembler-arm.cc | 4002 Register reg7, in AreAliased() argument
4006 reg7.is_valid() + reg8.is_valid(); in AreAliased()
4015 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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| D | macro-assembler-arm.h | 63 Register reg7 = no_reg,
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| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.cc | 5365 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased() argument
5372 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
5400 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType() argument
5408 match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1); in AreSameSizeAndType()
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| D | assembler-a64.h | 413 const CPURegister& reg7 = NoReg,
427 const CPURegister& reg7 = NoCPUReg,
|
| /external/v8/src/x64/ |
| D | macro-assembler-x64.h | 61 Register reg7 = no_reg,
|
| D | macro-assembler-x64.cc | 4990 Register reg7, in AreAliased() argument
4994 reg7.is_valid() + reg8.is_valid(); in AreAliased()
5003 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
|
| /external/v8/src/mips64/ |
| D | macro-assembler-mips64.cc | 5986 Register reg7, in AreAliased() argument
5990 reg7.is_valid() + reg8.is_valid(); in AreAliased()
5999 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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| D | macro-assembler-mips64.h | 99 Register reg7 = no_reg,
|
| /external/v8/src/mips/ |
| D | macro-assembler-mips.cc | 6001 Register reg7, in AreAliased() argument
6005 reg7.is_valid() + reg8.is_valid(); in AreAliased()
6014 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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| D | macro-assembler-mips.h | 93 Register reg7 = no_reg,
|