Searched refs:regsOverlap (Results 1 – 16 of 16) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64DeadRegisterDefinitionsPass.cpp | 56 if (TRI->regsOverlap(Reg, MO.getReg())) in implicitlyDefinesOverlappingReg()
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| D | AArch64PBQPRegAlloc.cpp | 197 if (livesOverlap && TRI->regsOverlap(pRd, pRa)) in addIntraChainConstraint()
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| D | AArch64AsmPrinter.cpp | 245 assert(RI->regsOverlap(RegToPrint, Reg)); in printAsmRegInClass()
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| /external/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 108 !TRI->regsOverlap(Reg, UserReg)) in processImplicitDef()
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| D | CriticalAntiDepBreaker.cpp | 410 if (TRI->regsOverlap(NewReg, *it)) { in findSuitableFreeRegister()
603 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
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| D | MachineInstrBundle.cpp | 303 bool IsRegOrOverlapping = MOReg == Reg || TRI->regsOverlap(MOReg, Reg); in analyzePhysReg()
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| D | RegAllocPBQP.cpp | 384 if (TRI.regsOverlap(PRegN, PRegM)) { in createInterferenceEdge()
548 if (TRI.regsOverlap(reg, CSR[i])) in isACalleeSavedRegister()
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| D | MachineCSE.cpp | 195 if (!TRI->regsOverlap(MO.getReg(), Reg)) in isPhysDefTriviallyDead()
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| D | MachineInstr.cpp | 1191 Found = TRI->regsOverlap(MOReg, Reg); in findRegisterDefOperandIdx()
1905 [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); })) in setPhysRegsDeadExcept()
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| D | TwoAddressInstructionPass.cpp | 542 return TRI->regsOverlap(RegA, RegB); in regsAreCompatible()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 403 bool regsOverlap(unsigned regA, unsigned regB) const { in regsOverlap() function
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 145 if (MOReg == Reg || TRI->regsOverlap(MOReg, Reg)) { in getRegReferences()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1548 (TRI->regsOverlap(EvenReg, BaseReg))) { in FixInvalidRegPairOp()
1549 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1648 if (TRI->regsOverlap(Reg, I->MBBI->getOperand(0).getReg())) { in LoadStoreMultipleOpti()
1927 if (MO.isDef() && TRI->regsOverlap(Reg, Base)) in IsSafeAndProfitableToMove()
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| D | ARMBaseInstrInfo.cpp | 838 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { in copyPhysReg()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 2737 if (TRI->regsOverlap(*ImpDef, PI->getReg()) && in canClobberReachingPhysRegUse()
2776 if (TRI->regsOverlap(Reg, SUReg)) in canClobberPhysRegDefs()
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 1387 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) { in assignCalleeSavedSpillSlots()
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