Searched refs:setRegClass (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/lib/Target/R600/ |
| D | SILowerI1Copies.cpp | 92 MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass); in runOnMachineFunction()
148 MRI.setRegClass(Reg, &AMDGPU::VGPR_32RegClass); in runOnMachineFunction()
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| D | SIISelLowering.cpp | 1968 MRI.setRegClass(VReg, RC); in AdjustInstrPostInstrSelection()
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| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 41 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
59 setRegClass(Reg, NewRC); in constrainRegClass()
84 setRegClass(Reg, NewRC); in recomputeRegClass()
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| D | MachineLICM.cpp | 1347 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]); in EliminateCSE()
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| D | RegisterCoalescer.cpp | 961 MRI->setRegClass(DstReg, NewRC); in reMaterializeTrivialDef()
1376 MRI->setRegClass(CP.getDstReg(), CP.getNewRC()); in joinCopy()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.cpp | 254 MRI.setRegClass(MO.getReg(), newRegClass); in convertToISA()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 393 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1183 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1187 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1200 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1209 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2278 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2280 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 586 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 628 MRI->setRegClass(NewVReg, SRC); in EmitRegSequence()
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