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Searched refs:sminv (Results 1 – 13 of 13) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Darm64-sminv.ll5 ; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
9 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a1)
16 ; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
20 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a1)
32 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a1)
38 ; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
42 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a1)
49 ; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
53 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a1)
60 ; CHECK: sminv.4s [[REGNUM:s[0-9]+]], v0
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Darm64-neon-across.ll27 declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)
29 declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)
31 declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)
37 declare i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16>)
39 declare i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8>)
255 ; CHECK: sminv b{{[0-9]+}}, {{v[0-9]+}}.8b
257 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a)
258 %0 = trunc i32 %sminv.i to i8
264 ; CHECK: sminv h{{[0-9]+}}, {{v[0-9]+}}.4h
266 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a)
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/external/llvm/test/MC/AArch64/
Dneon-across.s45 sminv b0, v1.8b
46 sminv b0, v1.16b
47 sminv h0, v1.4h
48 sminv h0, v1.8h
49 sminv s0, v1.4s
Dneon-diagnostics.s3774 sminv s0, v1.2s
3796 sminv d0, v1.2d define
/external/vixl/src/vixl/a64/
Dsimulator-a64.h1884 LogicVRegister sminv(VectorFormat vform,
Dmacro-assembler-a64.h2271 V(sminv, Sminv) \
Dassembler-a64.h2968 void sminv(const VRegister& vd,
Dsimulator-a64.cc2837 case NEON_SMINV: sminv(vf, rd, rn); break; in VisitNEONAcrossLanes()
Dlogic-a64.cc1478 LogicVRegister Simulator::sminv(VectorFormat vform, in sminv() function in vixl::Simulator
Dassembler-a64.cc4034 V(sminv, NEON_SMINV, true) \
/external/vixl/test/
Dtest-simulator-a64.cc4031 DEFINE_TEST_NEON_ACROSS(sminv, Basic)
/external/vixl/doc/
Dsupported-instructions.md3148 void sminv(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3828 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;