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Searched refs:umaxv (Results 1 – 14 of 14) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Darm64-umaxv.ll5 ; CHECK: umaxv.8b b[[REG:[0-9]+]], v0
10 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a) nounwind
28 ; CHECK: umaxv.4h h[[REG:[0-9]+]], v0
33 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) nounwind
49 ; CHECK: umaxv.8h h[[REG:[0-9]+]], v0
54 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) nounwind
70 ; CHECK: umaxv.16b b[[REG:[0-9]+]], v0
75 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a) nounwind
91 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
95 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)
[all …]
Darm64-neon-across.ll41 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>)
43 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>)
45 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>)
53 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>)
55 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>)
185 ; CHECK: umaxv b{{[0-9]+}}, {{v[0-9]+}}.8b
187 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a)
188 %0 = trunc i32 %umaxv.i to i8
194 ; CHECK: umaxv h{{[0-9]+}}, {{v[0-9]+}}.4h
196 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a)
[all …]
Darm64-vecCmpBr.ll58 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
66 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
82 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
89 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
105 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
112 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
128 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
135 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
195 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) #2
197 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) #2
/external/llvm/test/MC/AArch64/
Dneon-across.s57 umaxv b0, v1.8b
58 umaxv b0, v1.16b
59 umaxv h0, v1.4h
60 umaxv h0, v1.8h
61 umaxv s0, v1.4s
Dneon-diagnostics.s3775 umaxv s0, v1.2s
3797 umaxv d0, v1.2d define
/external/vixl/src/vixl/a64/
Dsimulator-a64.h2037 LogicVRegister umaxv(VectorFormat vform,
Dmacro-assembler-a64.h2284 V(umaxv, Umaxv) \
Dassembler-a64.h3128 void umaxv(const VRegister& vd,
Dsimulator-a64.cc2838 case NEON_UMAXV: umaxv(vf, rd, rn); break; in VisitNEONAcrossLanes()
Dlogic-a64.cc1585 LogicVRegister Simulator::umaxv(VectorFormat vform, in umaxv() function in vixl::Simulator
Dassembler-a64.cc4035 V(umaxv, NEON_UMAXV, true) \
/external/vixl/test/
Dtest-simulator-a64.cc4034 DEFINE_TEST_NEON_ACROSS(umaxv, Basic)
/external/vixl/doc/
Dsupported-instructions.md4158 void umaxv(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3829 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;