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Searched refs:v16f32 (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Davx512-round.ll6 %res = call <16 x float> @llvm.floor.v16f32(<16 x float> %a)
9 declare <16 x float> @llvm.floor.v16f32(<16 x float> %p)
22 %res = call <16 x float> @llvm.ceil.v16f32(<16 x float> %a)
25 declare <16 x float> @llvm.ceil.v16f32(<16 x float> %p)
38 %res = call <16 x float> @llvm.trunc.v16f32(<16 x float> %a)
41 declare <16 x float> @llvm.trunc.v16f32(<16 x float> %p)
54 %res = call <16 x float> @llvm.rint.v16f32(<16 x float> %a)
57 declare <16 x float> @llvm.rint.v16f32(<16 x float> %p)
70 %res = call <16 x float> @llvm.nearbyint.v16f32(<16 x float> %a)
73 declare <16 x float> @llvm.nearbyint.v16f32(<16 x float> %p)
Dwide-fma-contraction.ll25 …%ret = tail call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> …
29 declare <16 x float> @llvm.fmuladd.v16f32(<16 x float>, <16 x float>, <16 x float>) nounwind readno…
Dmasked_memop.ll65 …%res = call <16 x float> @llvm.masked.load.v16f32(<16 x float>* %addr, i32 4, <16 x i1>%mask, <16 …
170 call void @llvm.masked.store.v16f32(<16 x float>%val, <16 x float>* %addr, i32 4, <16 x i1>%mask)
250 declare void @llvm.masked.store.v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
252 declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)
Davx512-arith.ll395 declare <16 x float> @llvm.sqrt.v16f32(<16 x float>)
401 %b = call <16 x float> @llvm.sqrt.v16f32(<16 x float> %a)
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h100 v16f32 = 49, // 16 x f32 enumerator
240 return (SimpleTy == MVT::v8f64 || SimpleTy == MVT::v16f32 || in is512BitVector()
320 case v16f32: return f32; in getVectorElementType()
342 case v16f32: return 16; in getVectorNumElements()
443 case v16f32: in getSizeInBits()
575 if (NumElements == 16) return MVT::v16f32; in getVectorVT()
DValueTypes.td73 def v16f32 : ValueType<512, 49>; // 16 x f32 vector value
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp124 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
125 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
126 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
127 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
151 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
152 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()
/external/llvm/lib/Target/X86/
DX86CallingConv.td57 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
111 CCIfType<[v16f32, v8f64, v16i32, v8i64],
138 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
277 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
297 CCIfType<[v16i32, v8i64, v16f32, v8f64],
320 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
363 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
465 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
476 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
523 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
DX86InstrAVX512.td88 // The corresponding float type, e.g. v16f32 for v16i32
297 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
298 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
299 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
300 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
301 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
302 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
307 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
309 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
317 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
[all …]
DX86TargetTransformInfo.cpp498 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, in getCastInstrCost()
500 { ISD::FP_ROUND, MVT::v16f32, MVT::v8f64, 3 }, in getCastInstrCost()
519 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
520 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, in getCastInstrCost()
521 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, in getCastInstrCost()
522 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
701 { ISD::SETCC, MVT::v16f32, 1 }, in getCmpSelInstrCost()
DX86InstrFragmentsSIMD.td372 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
456 (v16f32 (alignedload512 node:$ptr))>;
548 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
DX86ISelLowering.cpp1244 addRegisterClass(MVT::v16f32, &X86::VR512RegClass); in X86TargetLowering()
1260 setOperationAction(ISD::LOAD, MVT::v16f32, Legal); in X86TargetLowering()
1266 setOperationAction(ISD::FADD, MVT::v16f32, Legal); in X86TargetLowering()
1267 setOperationAction(ISD::FSUB, MVT::v16f32, Legal); in X86TargetLowering()
1268 setOperationAction(ISD::FMUL, MVT::v16f32, Legal); in X86TargetLowering()
1269 setOperationAction(ISD::FDIV, MVT::v16f32, Legal); in X86TargetLowering()
1270 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal); in X86TargetLowering()
1271 setOperationAction(ISD::FNEG, MVT::v16f32, Custom); in X86TargetLowering()
1280 setOperationAction(ISD::FMA, MVT::v16f32, Legal); in X86TargetLowering()
1321 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal); in X86TargetLowering()
[all …]
/external/llvm/test/CodeGen/R600/
Dftrunc.ll10 declare <16 x float> @llvm.trunc.v16f32(<16 x float>) nounwind readnone
117 %y = call <16 x float> @llvm.trunc.v16f32(<16 x float> %x) nounwind readnone
Dfceil.ll10 declare <16 x float> @llvm.ceil.v16f32(<16 x float>) nounwind readnone
129 %y = call <16 x float> @llvm.ceil.v16f32(<16 x float> %x) nounwind readnone
Dfmaxnum.ll8 declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>) #0
118 %val = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b) #0
Dfminnum.ll9 declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #0
117 %val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b) #0
/external/llvm/test/Analysis/CostModel/X86/
Dmasked-intrinsic-cost.ll77 declare void @llvm.masked.store.v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
79 declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)
/external/llvm/lib/IR/
DValueTypes.cpp167 case MVT::v16f32: return "v16f32"; in getEVTString()
235 case MVT::v16f32: return VectorType::get(Type::getFloatTy(Context), 16); in getTypeForEVT()
/external/llvm/lib/Target/R600/
DSIRegisterInfo.td215 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
DSIISelLowering.cpp61 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass); in SITargetLowering()
68 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); in SITargetLowering()
178 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32}) { in SITargetLowering()
DAMDGPUISelLowering.cpp159 setOperationAction(ISD::STORE, MVT::v16f32, Promote); in AMDGPUTargetLowering()
160 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
199 setOperationAction(ISD::LOAD, MVT::v16f32, Promote); in AMDGPUTargetLowering()
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
DSIInstructions.td2581 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2584 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2618 def : BitConvert <v16i32, v16f32, VReg_512>;
2619 def : BitConvert <v16f32, v16i32, VReg_512>;
3189 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
/external/llvm/test/Transforms/LoopVectorize/X86/
Dmasked_load_store.ll114 ;AVX512: call <16 x float> @llvm.masked.load.v16f32
116 ;AVX512: call void @llvm.masked.store.v16f32
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp718 DecodeUNPCKLMask(MVT::v16f32, ShuffleMask); in EmitAnyX86InstComments()
770 DecodeUNPCKHMask(MVT::v16f32, ShuffleMask); in EmitAnyX86InstComments()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp109 case MVT::v16f32: return "MVT::v16f32"; in getEnumName()

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