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Searched refs:v16i32 (Results 1 – 23 of 23) sorted by relevance

/external/llvm/lib/Target/X86/
DX86InstrAVX512.td55 // Size of the element type in bits, e.g. 32 for v16i32.
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
88 // The corresponding float type, e.g. v16f32 for v16i32
294 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
299 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
303 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
308 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
309 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
310 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
311 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
[all …]
DX86TargetTransformInfo.cpp128 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
129 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
130 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
502 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, in getCastInstrCost()
503 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, in getCastInstrCost()
506 { ISD::TRUNCATE, MVT::v16i32, MVT::v8i64, 4 }, in getCastInstrCost()
509 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
510 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
512 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
513 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
[all …]
DX86CallingConv.td57 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
111 CCIfType<[v16f32, v8f64, v16i32, v8i64],
138 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
277 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
297 CCIfType<[v16i32, v8i64, v16f32, v8f64],
320 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
363 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
465 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
476 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
523 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
DX86InstrFragmentsSIMD.td376 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
458 (v16i32 (alignedload512 node:$ptr))>;
545 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
DX86ISelLowering.cpp1243 addRegisterClass(MVT::v16i32, &X86::VR512RegClass); in X86TargetLowering()
1263 setOperationAction(ISD::LOAD, MVT::v16i32, Legal); in X86TargetLowering()
1292 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal); in X86TargetLowering()
1293 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal); in X86TargetLowering()
1296 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal); in X86TargetLowering()
1301 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal); in X86TargetLowering()
1313 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1315 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1335 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom); in X86TargetLowering()
1354 setOperationAction(ISD::ADD, MVT::v16i32, Legal); in X86TargetLowering()
[all …]
DX86RegisterInfo.td457 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 512,
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h83 v16i32 = 36, // 16 x i32 enumerator
242 SimpleTy == MVT::v8i64 || SimpleTy == MVT::v16i32); in is512BitVector()
307 case v16i32: return i32; in getVectorElementType()
340 case v16i32: in getVectorNumElements()
441 case v16i32: in getSizeInBits()
556 if (NumElements == 16) return MVT::v16i32; in getVectorVT()
DValueTypes.td59 def v16i32 : ValueType<512, 36>; // 16 x i32 vector value
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp97 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
98 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
101 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
126 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
127 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
279 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 }, in getCmpSelInstrCost()
/external/llvm/test/CodeGen/X86/
Dmasked_memop.ll22 …%res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i3…
35 …%res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i3…
52 call void @llvm.masked.store.v16i32(<16 x i32>%val, <16 x i32>* %addr, i32 4, <16 x i1>%mask)
242 declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)
245 declare void @llvm.masked.store.v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
Davx512-intrinsics.ll327 %res = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %a, i1 false)
331 declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>, i1) nounwind readonly
/external/llvm/test/Analysis/CostModel/X86/
Dmasked-intrinsic-cost.ll69 declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)
72 declare void @llvm.masked.store.v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
/external/llvm/lib/IR/
DValueTypes.cpp154 case MVT::v16i32: return "v16i32"; in getEVTString()
222 case MVT::v16i32: return VectorType::get(Type::getInt32Ty(Context), 16); in getTypeForEVT()
/external/llvm/lib/Target/R600/
DSIRegisterInfo.td202 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 512, (add SGPR_512)>;
215 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
DSIISelLowering.cpp60 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass); in SITargetLowering()
67 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); in SITargetLowering()
85 setOperationAction(ISD::LOAD, MVT::v16i32, Custom); in SITargetLowering()
88 setOperationAction(ISD::STORE, MVT::v16i32, Custom); in SITargetLowering()
161 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand); in SITargetLowering()
178 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32}) { in SITargetLowering()
DSIInstructions.td2166 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
2176 defm : SMRD_Pattern_vi <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
2272 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
2465 v16i32>;
2574 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2577 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2618 def : BitConvert <v16i32, v16f32, VReg_512>;
2619 def : BitConvert <v16f32, v16i32, VReg_512>;
3194 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
DAMDGPUISelLowering.cpp160 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
/external/llvm/test/CodeGen/R600/
Dctpop.ll9 declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) nounwind readnone
170 %ctpop = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %val) nounwind readnone
/external/llvm/test/Transforms/LoopVectorize/X86/
Dmasked_load_store.ll30 ;AVX512: call <16 x i32> @llvm.masked.load.v16i32
32 ;AVX512: call void @llvm.masked.store.v16i32
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp361 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 * AmortizationCost }, in getCmpSelInstrCost()
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp502 DecodeUNPCKHMask(MVT::v16i32, ShuffleMask); in EmitAnyX86InstComments()
591 DecodeUNPCKLMask(MVT::v16i32, ShuffleMask); in EmitAnyX86InstComments()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp96 case MVT::v16i32: return "MVT::v16i32"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td177 def llvm_v16i32_ty : LLVMType<v16i32>; // 16 x i32