Searched refs:v2i1 (Results 1 – 15 of 15) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 59 v2i1 = 13, // 2 x i1 enumerator
90 FIRST_INTEGER_VECTOR_VALUETYPE = v2i1,
109 FIRST_VECTOR_VALUETYPE = v2i1,
284 case v2i1 : in getVectorElementType()
359 case v2i1: in getVectorNumElements()
393 case v2i1: return 2; in getSizeInBits()
527 if (NumElements == 2) return MVT::v2i1; in getVectorVT()
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| D | ValueTypes.td | 36 def v2i1 : ValueType<2 , 13>; // 2 x i1 vector value
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoVector.td | 14 def V2I1: PatLeaf<(v2i1 PredRegs:$R)>;
233 def: vcmp_vi1_pat<A2_vcmpweq, seteq, V2I32, v2i1>;
234 def: vcmp_vi1_pat<A2_vcmpwgt, setgt, V2I32, v2i1>;
235 def: vcmp_vi1_pat<A2_vcmpwgtu, setugt, V2I32, v2i1>;
317 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, v2i1>;
324 def: InvertCmp_pat<A2_vcmpwgtu, setult, V2I32, v2i1>;
328 def: Pat<(v2i1 (setne V2I32:$Rs, V2I32:$Rt)),
329 (C2_not (v2i1 (A2_vcmpbeq V2I32:$Rs, V2I32:$Rt)))>;
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| D | HexagonRegisterInfo.td | 178 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32,
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| D | HexagonISelLowering.cpp | 1011 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp); in LowerSETCC()
1260 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa in HexagonTargetLowering()
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 131 case MVT::v2i1: return "v2i1"; in getEVTString()
199 case MVT::v2i1: return VectorType::get(Type::getInt1Ty(Context), 2); in getTypeForEVT()
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 473 def VK2 : RegisterClass<"X86", [v2i1], 8, (add VK1)> {let Size = 8;}
481 def VK2WM : RegisterClass<"X86", [v2i1], 8, (sub VK2, K0)> {let Size = 8;}
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| D | X86InstrAVX512.td | 2065 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2067 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2071 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2072 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
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| D | X86ISelLowering.cpp | 1460 addRegisterClass(MVT::v2i1, &X86::VK2RegClass); in X86TargetLowering()
1463 setOperationAction(ISD::SETCC, MVT::v2i1, Custom); in X86TargetLowering()
1624 case 2: return MVT::v2i1; in getSetCCResultType()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 73 case MVT::v2i1: return "MVT::v2i1"; in getEnumName()
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 102 setOperationAction(ISD::SETCC, MVT::v2i1, Expand); in SITargetLowering()
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom); in SITargetLowering()
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| D | R600ISelLowering.cpp | 98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
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| D | AMDGPUISelLowering.cpp | 183 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand); in AMDGPUTargetLowering()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 152 def llvm_v2i1_ty : LLVMType<v2i1>; // 2 x i1
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 61 case MVT::v2i1: in IsPTXVectorType()
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