1//===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the Hexagon register file. 12//===----------------------------------------------------------------------===// 13 14let Namespace = "Hexagon" in { 15 16 class HexagonReg<bits<5> num, string n, list<string> alt = [], 17 list<Register> alias = []> : Register<n> { 18 field bits<5> Num; 19 let Aliases = alias; 20 let HWEncoding{4-0} = num; 21 } 22 23 class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs, 24 list<string> alt = []> : 25 RegisterWithSubRegs<n, subregs> { 26 field bits<5> Num; 27 28 let AltNames = alt; 29 let HWEncoding{4-0} = num; 30 } 31 32 // Registers are identified with 5-bit ID numbers. 33 // Ri - 32-bit integer registers. 34 class Ri<bits<5> num, string n, list<string> alt = []> : HexagonReg<num, n, alt> { 35 let Num = num; 36 } 37 38 // Rf - 32-bit floating-point registers. 39 class Rf<bits<5> num, string n> : HexagonReg<num, n> { 40 let Num = num; 41 } 42 43 44 // Rd - 64-bit registers. 45 class Rd<bits<5> num, string n, list<Register> subregs> : 46 HexagonDoubleReg<num, n, subregs> { 47 let Num = num; 48 let SubRegs = subregs; 49 } 50 51 // Rp - predicate registers 52 class Rp<bits<5> num, string n> : HexagonReg<num, n> { 53 let Num = num; 54 } 55 56 // Rc - control registers 57 class Rc<bits<5> num, string n, 58 list<string> alt = [], list<Register> alias = []> : 59 HexagonReg<num, n, alt, alias> { 60 let Num = num; 61 } 62 63 // Rcc - 64-bit control registers. 64 class Rcc<bits<5> num, string n, list<Register> subregs, 65 list<string> alt = []> : 66 HexagonDoubleReg<num, n, subregs, alt> { 67 let Num = num; 68 let SubRegs = subregs; 69 } 70 71 // Mx - address modifier registers 72 class Mx<bits<1> num, string n> : HexagonReg<{0b0000, num}, n> { 73 let Num = !cast<bits<5>>(num); 74 } 75 76 def subreg_loreg : SubRegIndex<32>; 77 def subreg_hireg : SubRegIndex<32, 32>; 78 def subreg_overflow : SubRegIndex<1, 0>; 79 80 // Integer registers. 81 foreach i = 0-28 in { 82 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>; 83 } 84 85 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>; 86 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>; 87 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>; 88 89 // Aliases of the R* registers used to hold 64-bit int values (doubles). 90 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in { 91 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; 92 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; 93 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; 94 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>; 95 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>; 96 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>; 97 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>; 98 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>; 99 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>; 100 def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>; 101 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>; 102 def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>; 103 def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>; 104 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>; 105 def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>; 106 def D15 : Rd<30, "r31:30", [R30, R31]>, DwarfRegNum<[62]>; 107 } 108 109 // Predicate registers. 110 def P0 : Rp<0, "p0">, DwarfRegNum<[63]>; 111 def P1 : Rp<1, "p1">, DwarfRegNum<[64]>; 112 def P2 : Rp<2, "p2">, DwarfRegNum<[65]>; 113 def P3 : Rp<3, "p3">, DwarfRegNum<[66]>; 114 115 // Modifier registers. 116 // C6 and C7 can also be M0 and M1, but register names must be unique, even 117 // if belonging to different register classes. 118 def M0 : Mx<0, "m0">, DwarfRegNum<[72]>; 119 def M1 : Mx<1, "m1">, DwarfRegNum<[73]>; 120 121 // Fake register to represent USR.OVF bit. Artihmetic/saturating instruc- 122 // tions modify this bit, and multiple such instructions are allowed in the 123 // same packet. We need to ignore output dependencies on this bit, but not 124 // on the entire USR. 125 def USR_OVF : Rc<?, "usr.ovf">; 126 127 // Control registers. 128 def SA0 : Rc<0, "sa0", ["c0"]>, DwarfRegNum<[67]>; 129 def LC0 : Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>; 130 def SA1 : Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>; 131 def LC1 : Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>; 132 def P3_0 : Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>, 133 DwarfRegNum<[71]>; 134 def C6 : Rc<6, "c6", [], [M0]>, DwarfRegNum<[72]>; 135 def C7 : Rc<7, "c7", [], [M1]>, DwarfRegNum<[73]>; 136 137 def USR : Rc<8, "usr", ["c8"]>, DwarfRegNum<[74]> { 138 let SubRegIndices = [subreg_overflow]; 139 let SubRegs = [USR_OVF]; 140 } 141 def PC : Rc<9, "pc">, DwarfRegNum<[75]>; 142 def UGP : Rc<10, "ugp", ["c10"]>, DwarfRegNum<[76]>; 143 def GP : Rc<11, "gp">, DwarfRegNum<[77]>; 144 def CS0 : Rc<12, "cs0", ["c12"]>, DwarfRegNum<[78]>; 145 def CS1 : Rc<13, "cs1", ["c13"]>, DwarfRegNum<[79]>; 146 def UPCL : Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[80]>; 147 def UPCH : Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[81]>; 148} 149 150 // Control registers pairs. 151 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in { 152 def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>; 153 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>; 154 def C7_6 : Rcc<6, "c7:6", [C6, C7], ["m1:0"]>, DwarfRegNum<[72]>; 155 def C9_8 : Rcc<8, "c9:8", [USR, PC]>, DwarfRegNum<[74]>; 156 def C11_10 : Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>; 157 def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>; 158 def UPC : Rcc<14, "c15:14", [UPCL, UPCH]>, DwarfRegNum<[80]>; 159 } 160 161// Register classes. 162// 163// FIXME: the register order should be defined in terms of the preferred 164// allocation order... 165// 166def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, 167 (add (sequence "R%u", 0, 9), 168 (sequence "R%u", 12, 28), 169 R10, R11, R29, R30, R31)> { 170} 171 172def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, 173 (add (sequence "D%u", 0, 4), 174 (sequence "D%u", 6, 13), D5, D14, D15)>; 175 176 177def PredRegs : RegisterClass<"Hexagon", 178 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, 179 (add (sequence "P%u", 0, 3))> 180{ 181 let Size = 32; 182} 183 184let Size = 32 in 185def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>; 186 187let Size = 32, isAllocatable = 0 in 188def CtrRegs : RegisterClass<"Hexagon", [i32], 32, 189 (add LC0, SA0, LC1, SA1, 190 P3_0, 191 M0, M1, C6, C7, CS0, CS1, UPCL, UPCH, 192 USR, USR_OVF, UGP, GP, PC)>; 193 194let Size = 64, isAllocatable = 0 in 195def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64, 196 (add C1_0, C3_2, C7_6, C9_8, C11_10, CS, UPC)>; 197 198def VolatileV3 { 199 list<Register> Regs = [D0, D1, D2, D3, D4, D5, D6, D7, 200 R28, R31, 201 P0, P1, P2, P3, 202 M0, M1, 203 LC0, LC1, SA0, SA1, USR, USR_OVF]; 204} 205 206def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a), 207[{ 208 return isPositiveHalfWord(N); 209}]>; 210