| /external/clang/test/CodeGen/ |
| D | systemz-abi-vector.c | 7 typedef __attribute__((vector_size(2))) char v2i8; typedef
36 v2i8 pass_v2i8(v2i8 arg) { return arg; } in pass_v2i8()
126 v2i8 va_v2i8(__builtin_va_list l) { return __builtin_va_arg(l, v2i8); } in va_v2i8()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 200 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
203 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
214 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
217 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
233 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
236 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
247 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 2 }, in getCastInstrCost()
250 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 2 }, in getCastInstrCost()
|
| D | AArch64ISelLowering.cpp | 1735 case MVT::v2i8: in getExtensionTo64Bits()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 67 v2i8 = 20, // 2 x i8 enumerator
204 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
291 case v2i8 : in getVectorElementType()
360 case v2i8: in getVectorNumElements()
401 case v2i8: in getSizeInBits()
536 if (NumElements == 2) return MVT::v2i8; in getVectorVT()
|
| D | ValueTypes.td | 43 def v2i8 : ValueType<16 , 20>; // 2 x i8 vector value
|
| /external/llvm/test/CodeGen/Hexagon/vect/ |
| D | vect-load-1.ll | 2 …16f76e0<LD2[undef](align=8), sext from v2i8>", 0x16c5890, 0x16f76e0, 0x16f76e0<LD2[undef](align=8)…
|
| /external/llvm/test/CodeGen/ARM/ |
| D | 2012-08-23-legalize-vmull.ll | 26 ; v2i8
70 ; v2i8
120 ; v2i8
121 ; v2i8 x v2i16
|
| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsNVVM.td | 1871 "llvm.nvvm.suld.1d.v2i8.clamp">;
1916 "llvm.nvvm.suld.1d.array.v2i8.clamp">;
1961 "llvm.nvvm.suld.2d.v2i8.clamp">;
2006 "llvm.nvvm.suld.2d.array.v2i8.clamp">;
2051 "llvm.nvvm.suld.3d.v2i8.clamp">;
2097 "llvm.nvvm.suld.1d.v2i8.trap">;
2142 "llvm.nvvm.suld.1d.array.v2i8.trap">;
2187 "llvm.nvvm.suld.2d.v2i8.trap">;
2232 "llvm.nvvm.suld.2d.array.v2i8.trap">;
2277 "llvm.nvvm.suld.3d.v2i8.trap">;
[all …]
|
| D | Intrinsics.td | 159 def llvm_v2i8_ty : LLVMType<v2i8>; // 2 x i8
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 108 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
109 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
140 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
141 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
|
| D | ARMInstrNEON.td | 6736 // v2i8 -> v2i16 -> v2i32
6748 // v2i8 -> v2i16 -> v2i32
6754 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
|
| D | ARMISelLowering.cpp | 574 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16, in ARMTargetLowering()
5761 case MVT::v2i8: in getExtensionTo64Bits()
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 57 (int)MVT::v2i8, in InitAMDILLowering()
85 (int)MVT::v2i8, in InitAMDILLowering()
207 setOperationAction(ISD::UDIV, MVT::v2i8, Expand); in InitAMDILLowering()
648 if (OVT == MVT::v2i8) { in LowerSREM8()
|
| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 138 case MVT::v2i8: return "v2i8"; in getEVTString()
206 case MVT::v2i8: return VectorType::get(Type::getInt8Ty(Context), 2); in getTypeForEVT()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoVector.td | 362 // Sign extends a v2i8 into a v2i32.
363 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)),
466 // Zero and sign extended load from v2i8 into v2i16.
468 [{ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; }]>;
471 [{ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; }]>;
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 41 // Extract v2i8
46 (v2i8 V2I8Regs:$src), imm:$c))],
107 // Insert v2i8
799 def : Pat<(v2i8 (vec_shuf:$op V2I8Regs:$src1, V2I8Regs:$src2)),
890 def : Pat<(v2i8 (extract_subvec V4I8Regs:$src, 0)),
893 def : Pat<(v2i8 (extract_subvec V4I8Regs:$src, 2)),
1265 // v2i8 -> i16
1289 // i16 -> v2i8
|
| D | NVPTXISelLowering.cpp | 63 case MVT::v2i8: in IsPTXVectorType()
1876 case MVT::v2i8: in LowerSTOREVector()
3996 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) { in PerformANDCombine()
4234 case MVT::v2i8: in ReplaceLoadVector()
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 80 case MVT::v2i8: return "MVT::v2i8"; in getEnumName()
|
| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 173 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom); in AMDGPUTargetLowering()
228 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
229 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
230 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
|
| D | SIISelLowering.cpp | 112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); in SITargetLowering()
|
| D | R600ISelLowering.cpp | 103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); in R600TargetLowering()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 871 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom); in X86TargetLowering()
959 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom); in X86TargetLowering()
967 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal); in X86TargetLowering()
974 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal); in X86TargetLowering()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 618 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); in PPCTargetLowering()
|