| /external/llvm/test/CodeGen/AArch64/ |
| D | fp16-vector-load-store.ll | 43 ; Load to one lane of v4f16
63 ; Simple store of v4f16
81 ; Store from one lane of v4f16
102 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0v4f16(<4 x half>*)
103 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0v4f16(<4 x half>*)
104 declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0v4f16(<4 …
105 declare void @llvm.aarch64.neon.st2.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>*)
106 declare void @llvm.aarch64.neon.st3.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>*)
107 declare void @llvm.aarch64.neon.st4.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>, <…
115 ; Load 2 x v4f16 with de-interleaving
[all …]
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| D | fp16-vector-nvcast.ll | 3 ; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src)))
14 ; Test pattern (v4f16 (AArch64NvCast (v4i16 FPR64:$src)))
25 ; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src)))
36 ; Test pattern (v4f16 (AArch64NvCast (f64 FPR64:$src)))
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| D | arm64-aapcs.ll | 127 ; Check that v4f16 can be passed and returned in registers
141 ; Check that v4f16 can be passed and returned on the stack
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 94 v4f16 = 43, // 4 x f16 enumerator
219 SimpleTy == MVT::v4f16 || SimpleTy == MVT::v2f32 || in is64BitVector()
314 case v4f16: in getVectorElementType()
356 case v4f16: in getVectorNumElements()
419 case v4f16: in getSizeInBits()
567 if (NumElements == 4) return MVT::v4f16; in getVectorVT()
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| D | ValueTypes.td | 67 def v4f16 : ValueType<64 , 43>; // 4 x f16 vector value
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 2262 else if (VT == MVT::v4i16 || VT == MVT::v4f16) in Select()
2280 else if (VT == MVT::v4i16 || VT == MVT::v4f16) in Select()
2298 else if (VT == MVT::v4i16 || VT == MVT::v4f16) in Select()
2316 else if (VT == MVT::v4i16 || VT == MVT::v4f16) in Select()
2334 else if (VT == MVT::v4i16 || VT == MVT::v4f16) in Select()
2352 else if (VT == MVT::v4i16 || VT == MVT::v4f16) in Select()
2370 else if (VT == MVT::v4i16 || VT == MVT::v4f16) in Select()
2388 else if (VT == MVT::v4i16 || VT == MVT::v4f16) in Select()
2406 else if (VT == MVT::v4i16 || VT == MVT::v4f16) in Select()
2422 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
[all …]
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| D | AArch64CallingConvention.td | 31 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
65 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
74 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
86 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
101 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
146 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
156 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
175 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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| D | AArch64InstrInfo.td | 1229 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1272 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1416 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1577 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1897 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1990 def : Pat<(store (v4f16 FPR64:$Rt),
2087 def : Pat<(store (v4f16 FPR64:$Rt),
2199 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2253 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2573 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
[all …]
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| D | AArch64ISelLowering.cpp | 110 addDRTypeForNEON(MVT::v4f16); in AArch64TargetLowering()
320 setOperationAction(ISD::FADD, MVT::v4f16, Promote); in AArch64TargetLowering()
321 setOperationAction(ISD::FSUB, MVT::v4f16, Promote); in AArch64TargetLowering()
322 setOperationAction(ISD::FMUL, MVT::v4f16, Promote); in AArch64TargetLowering()
323 setOperationAction(ISD::FDIV, MVT::v4f16, Promote); in AArch64TargetLowering()
324 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote); in AArch64TargetLowering()
325 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote); in AArch64TargetLowering()
326 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
327 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
328 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
[all …]
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| D | AArch64RegisterInfo.td | 393 v1i64, v4f16],
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| D | AArch64InstrFormats.td | 5273 def : Pat<(v4f16 (OpNode V64:$Rn, V64:$Rm)),
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 163 case MVT::v4f16: return "v4f16"; in getEVTString()
229 case MVT::v4f16: return VectorType::get(Type::getHalfTy(Context), 4); in getTypeForEVT()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 103 case MVT::v4f16: return "MVT::v4f16"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 185 def llvm_v4f16_ty : LLVMType<v4f16>; // 4 x half (__fp16)
|