1; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false < %s | FileCheck %s 2 3@var = global i32 0, align 4 4 5define i128 @test_i128_align(i32, i128 %arg, i32 %after) { 6 store i32 %after, i32* @var, align 4 7; CHECK: str w4, [{{x[0-9]+}}, :lo12:var] 8 9 ret i128 %arg 10; CHECK: mov x0, x2 11; CHECK: mov x1, x3 12} 13 14@var64 = global i64 0, align 8 15 16 ; Check stack slots are 64-bit at all times. 17define void @test_stack_slots([8 x i32], i1 %bool, i8 %char, i16 %short, 18 i32 %int, i64 %long) { 19 ; Part of last store. Blasted scheduler. 20; CHECK: ldr [[LONG:x[0-9]+]], [sp, #32] 21 22 %ext_bool = zext i1 %bool to i64 23 store volatile i64 %ext_bool, i64* @var64, align 8 24; CHECK: ldrb w[[EXT:[0-9]+]], [sp] 25; CHECK: and x[[EXTED:[0-9]+]], x[[EXT]], #0x1 26; CHECK: str x[[EXTED]], [{{x[0-9]+}}, :lo12:var64] 27 28 %ext_char = zext i8 %char to i64 29 store volatile i64 %ext_char, i64* @var64, align 8 30; CHECK: ldrb w[[EXT:[0-9]+]], [sp, #8] 31; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64] 32 33 %ext_short = zext i16 %short to i64 34 store volatile i64 %ext_short, i64* @var64, align 8 35; CHECK: ldrh w[[EXT:[0-9]+]], [sp, #16] 36; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64] 37 38 %ext_int = zext i32 %int to i64 39 store volatile i64 %ext_int, i64* @var64, align 8 40; CHECK: ldr{{b?}} w[[EXT:[0-9]+]], [sp, #24] 41; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64] 42 43 store volatile i64 %long, i64* @var64, align 8 44; CHECK: str [[LONG]], [{{x[0-9]+}}, :lo12:var64] 45 46 ret void 47} 48 49; Make sure the callee does extensions (in the absence of zext/sext 50; keyword on args) while we're here. 51 52define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) { 53 %ext_bool = zext i1 %bool to i64 54 store volatile i64 %ext_bool, i64* @var64 55; CHECK: and [[EXT:x[0-9]+]], x0, #0x1 56; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64] 57 58 %ext_char = sext i8 %char to i64 59 store volatile i64 %ext_char, i64* @var64 60; CHECK: sxtb [[EXT:x[0-9]+]], w1 61; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64] 62 63 %ext_short = zext i16 %short to i64 64 store volatile i64 %ext_short, i64* @var64 65; CHECK: and [[EXT:x[0-9]+]], x2, #0xffff 66; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64] 67 68 %ext_int = zext i32 %int to i64 69 store volatile i64 %ext_int, i64* @var64 70; CHECK: ubfx [[EXT:x[0-9]+]], x3, #0, #32 71; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64] 72 73 ret void 74} 75 76declare void @variadic(i32 %a, ...) 77 78 ; Under AAPCS variadic functions have the same calling convention as 79 ; others. The extra arguments should go in registers rather than on the stack. 80define void @test_variadic() { 81 call void(i32, ...) @variadic(i32 0, i64 1, double 2.0) 82; CHECK: fmov d0, #2.0 83; CHECK: orr w1, wzr, #0x1 84; CHECK: bl variadic 85 ret void 86} 87 88; We weren't marking x7 as used after deciding that the i128 didn't fit into 89; registers and putting the first half on the stack, so the *second* half went 90; into x7. Yuck! 91define i128 @test_i128_shadow([7 x i64] %x0_x6, i128 %sp) { 92; CHECK-LABEL: test_i128_shadow: 93; CHECK: ldp x0, x1, [sp] 94 95 ret i128 %sp 96} 97 98; This test is to check if fp128 can be correctly handled on stack. 99define fp128 @test_fp128([8 x float] %arg0, fp128 %arg1) { 100; CHECK-LABEL: test_fp128: 101; CHECK: ldr {{q[0-9]+}}, [sp] 102 ret fp128 %arg1 103} 104 105; Check if VPR can be correctly pass by stack. 106define <2 x double> @test_vreg_stack([8 x <2 x double>], <2 x double> %varg_stack) { 107entry: 108; CHECK-LABEL: test_vreg_stack: 109; CHECK: ldr {{q[0-9]+}}, [sp] 110 ret <2 x double> %varg_stack; 111} 112 113; Check that f16 can be passed and returned (ACLE 2.0 extension) 114define half @test_half(float, half %arg) { 115; CHECK-LABEL: test_half: 116; CHECK: mov v0.16b, v1.16b 117 ret half %arg; 118} 119 120; Check that f16 constants are materialized correctly 121define half @test_half_const() { 122; CHECK-LABEL: test_half_const: 123; CHECK: ldr h0, [x{{[0-9]+}}, :lo12:{{.*}}] 124 ret half 0xH4248 125} 126 127; Check that v4f16 can be passed and returned in registers 128define <4 x half> @test_v4_half_register(float, <4 x half> %arg) { 129; CHECK-LABEL: test_v4_half_register: 130; CHECK: mov v0.16b, v1.16b 131 ret <4 x half> %arg; 132} 133 134; Check that v8f16 can be passed and returned in registers 135define <8 x half> @test_v8_half_register(float, <8 x half> %arg) { 136; CHECK-LABEL: test_v8_half_register: 137; CHECK: mov v0.16b, v1.16b 138 ret <8 x half> %arg; 139} 140 141; Check that v4f16 can be passed and returned on the stack 142define <4 x half> @test_v4_half_stack([8 x <2 x double>], <4 x half> %arg) { 143; CHECK-LABEL: test_v4_half_stack: 144; CHECK: ldr d0, [sp] 145 ret <4 x half> %arg; 146} 147 148; Check that v8f16 can be passed and returned on the stack 149define <8 x half> @test_v8_half_stack([8 x <2 x double>], <8 x half> %arg) { 150; CHECK-LABEL: test_v8_half_stack: 151; CHECK: ldr q0, [sp] 152 ret <8 x half> %arg; 153} 154