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Searched refs:vcc (Results 1 – 25 of 43) sorted by relevance

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/external/llvm/test/MC/R600/
Dvopc.s9 v_cmp_lt_f32 vcc, s2, v4
13 v_cmp_lt_f32 vcc, 0, v4
17 v_cmp_lt_f32 vcc, 10.0, v4
21 v_cmp_lt_f32 vcc, v255, v255
25 v_cmp_lt_f32_e32 vcc, v2, v4
33 v_cmp_f_f32 vcc, v2, v4
36 v_cmp_lt_f32 vcc, v2, v4
/external/llvm/test/CodeGen/R600/
Dsetcc-opt.ll7 ; GCN: v_cmp_ne_i32_e32 vcc,
8 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
24 ; GCN: v_cmp_ne_i32_e32 vcc,
25 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
41 ; GCN: v_cmp_eq_i32_e32 vcc,
42 ; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, -1, vcc
43 ; GCN-NEXT: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}}
57 ; GCN: v_cmp_ne_i32_e32 vcc,
58 ; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, -1, vcc
59 ; GCN-NEXT: v_cmp_ne_i32_e32 vcc, 1, [[TMP]]{{$}}
[all …]
Dcommute-compares.ll10 ; GCN: v_cmp_eq_i32_e32 vcc, 64, v{{[0-9]+}}
23 ; GCN: v_cmp_ne_i32_e32 vcc, 64, v{{[0-9]+}}
38 ; GCN: v_cmp_ne_i32_e32 vcc, [[K]], v{{[0-9]+}}
51 ; GCN: v_cmp_lt_u32_e32 vcc, 64, v{{[0-9]+}}
64 ; GCN: v_cmp_lt_u32_e32 vcc, 63, v{{[0-9]+}}
77 ; GCN: v_cmp_gt_u32_e32 vcc, 64, v{{[0-9]+}}
90 ; GCN: v_cmp_gt_u32_e32 vcc, 64, v{{[0-9]+}}
106 ; GCN: v_cmp_gt_u32_e32 vcc, [[K]], v{{[0-9]+}}
119 ; GCN: v_cmp_lt_i32_e32 vcc, -1, v{{[0-9]+}}
132 ; GCN: v_cmp_lt_i32_e32 vcc, -3, v{{[0-9]+}}
[all …]
Dsetcc64.ll61 ; SI: v_cmp_lg_f64_e32 vcc
62 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
82 ; SI: v_cmp_nlg_f64_e32 vcc
83 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
94 ; SI: v_cmp_nle_f64_e32 vcc
95 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
105 ; SI: v_cmp_nlt_f64_e32 vcc
106 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
116 ; SI: v_cmp_nge_f64_e32 vcc
117 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
[all …]
Dfcmp64.ll5 ; CHECK: v_cmp_nge_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
17 ; CHECK: v_cmp_ngt_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
29 ; CHECK: v_cmp_nle_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
41 ; CHECK: v_cmp_nlt_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
53 ; CHECK: v_cmp_neq_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
65 ; CHECK: v_cmp_nlg_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
Dvalu-i1.ll45 ; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
46 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
71 ; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
72 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
82 ; SI: v_cmp_eq_i32_e32 vcc,
114 ; SI: v_cmp_lt_i32_e32 vcc
115 ; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc
129 ; SI-DAG: v_cmp_ne_i32_e32 [[NEG1_CHECK_1:vcc]], -1, [[B]]
137 ; SI: v_cmp_ge_i64_e32 vcc
138 ; SI: s_or_b64 [[COND_STATE]], vcc, [[COND_STATE]]
Dllvm.AMDGPU.class.ll13 ; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[VB]]
14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
103 ; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[MASK]]
104 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
117 ; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[MASK]]
118 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
131 ; SI: v_cmp_class_f32_e32 vcc, [[VA]], [[MASK]]
132 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
149 ; SI: v_cmp_class_f32_e32 vcc, 1.0, [[VB]]
150 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
[all …]
Dllvm.AMDGPU.div_fmas.ll81 ; SI: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}}
91 ; SI: s_mov_b64 vcc, 0
100 ; SI: s_mov_b64 vcc, -1
113 ; SI-DAG: v_cmp_eq_i32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}}
115 ; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
139 ; SI: v_cmp_eq_i32_e32 vcc, 0, v{{[0-9]+}}
140 ; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc
144 ; SI: v_cmp_ne_i32_e32 vcc, 0, [[LOAD]]
145 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
150 ; SI: v_cmp_ne_i32_e32 vcc, 0, v0
Dsetcc.ll100 ; SI: v_cmp_lg_f32_e32 vcc
101 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
132 ; SI: v_cmp_nlg_f32_e32 vcc
133 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
145 ; SI: v_cmp_nle_f32_e32 vcc
146 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
159 ; SI: v_cmp_nlt_f32_e32 vcc
160 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
173 ; SI: v_cmp_nge_f32_e32 vcc
174 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
[all …]
Dtrunc-cmp-constant.ll7 ; SI: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}}
8 ; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, vcc, -1{{$}}
23 ; SI: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}}
24 ; SI-NEXT: s_xor_b64 [[NEG:s\[[0-9]+:[0-9]+\]]], vcc, -1
120 ; SI: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}}
121 ; SI-NEXT: s_xor_b64 [[NEG:s\[[0-9]+:[0-9]+\]]], vcc, -1
160 ; SI: v_cmp_ne_i32_e32 vcc, -1, [[LOAD]]{{$}}
Dtrunc.ll76 ; SI: v_cmp_eq_i32_e32 vcc, 1, [[MASKED]]
77 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
88 ; SI: v_cmp_eq_i32_e32 vcc, 1, [[MASKED]]
89 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
Dfdiv.f64.ll10 ; CI-DAG: v_div_scale_f64 [[SCALE1:v\[[0-9]+:[0-9]+\]]], vcc, [[NUM]], [[DEN]], [[NUM]]
18 ; SI-DAG: v_cmp_eq_i32_e32 vcc, {{v[0-9]+}}, {{v[0-9]+}}
20 ; SI-DAG: s_xor_b64 vcc, [[CMP0]], vcc
Dsgpr-control-flow.ll67 ; SI: v_cmp_gt_i32_e32 [[CMP_IF:vcc]], 0, [[AVAL]]
72 ; SI: v_cmp_eq_i32_e32 [[CMP_ELSE:vcc]], 0, [[AVAL]]
75 ; SI: v_cmp_ne_i32_e32 [[CMP_CMP:vcc]], 0, [[V_CMP]]
Di1-copy-phi.ll9 ; SI: v_cmp_ne_i32_e32 vcc, 0, [[REG]]
Dfp-classify.ll12 ; SI: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
48 ; SI: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
Dsplit-scalar-i64-add.ll7 ; set in vcc, which is undefined since the low scalar half add sets
Dsign_extend.ll27 ; SI: v_cndmask_b32_e64 v[[LOREG:[0-9]+]], 0, -1, vcc
Dor.ll158 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
171 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
Dxor.ll43 ; SI-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 0, {{v[0-9]+}}
/external/kernel-headers/original/uapi/linux/
Datm_tcp.h37 atm_kptr_t vcc; /* both directions */ member
Datmsvc.h24 atm_kptr_t vcc; member
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstructions.td627 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
632 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
671 (ins VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1), "V_CNDMASK_B32",
673 (select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1))] > {
675 let DisableEncoding = "$vcc";
680 (f32 (select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1)),
681 (V_CNDMASK_B32 VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1)
854 [(set VCCReg:$vcc, (SIvcc_and SReg_64:$src0, SReg_64:$src1))]
980 (ins brtarget:$target, VCCReg:$vcc),
982 [(IL_brcond bb:$target, VCCReg:$vcc)]
[all …]
DSIInstrFormats.td45 : SOP2 <op, (outs VCCReg:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
/external/llvm/lib/Target/R600/
DAMDGPUInstrInfo.td38 // float, float, float, vcc
DSIRegisterInfo.td24 def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {

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