| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 130 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
133 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
141 { ISD::SRA, MVT::v4i32, 1 }, in getArithmeticInstrCost()
144 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
156 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized. in getArithmeticInstrCost()
157 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized. in getArithmeticInstrCost()
158 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized. in getArithmeticInstrCost()
205 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
206 { ISD::SRA, MVT::v8i16, 1 }, // psraw. in getArithmeticInstrCost()
207 { ISD::SRA, MVT::v4i32, 1 }, // psrad. in getArithmeticInstrCost()
[all …]
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| D | X86IntrinsicsInfo.h | 228 X86_INTRINSIC_DATA(avx2_psrav_d, INTR_TYPE_2OP, ISD::SRA, 0),
229 X86_INTRINSIC_DATA(avx2_psrav_d_256, INTR_TYPE_2OP, ISD::SRA, 0),
381 X86_INTRINSIC_DATA(avx512_mask_psrav_d, INTR_TYPE_2OP_MASK, ISD::SRA, 0),
382 X86_INTRINSIC_DATA(avx512_mask_psrav_q, INTR_TYPE_2OP_MASK, ISD::SRA, 0),
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| /external/pcre/dist/sljit/ |
| D | sljitNativeSPARC_32.c | 60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst)); in emit_single_op()
71 …return push_inst(compiler, (op == SLJIT_MOV_SH ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)); in emit_single_op()
112 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(dst) | IMM(31), DR(TMP_REG1))); in emit_single_op()
134 FAIL_IF(push_inst(compiler, SRA | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
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| D | sljitNativeMIPS_32.c | 91 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(24), DR(dst)); in emit_single_op()
109 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(16), DR(dst)); in emit_single_op()
312 FAIL_IF(push_inst(compiler, SRA | T(dst) | DA(UGREATER_FLAG) | SH_IMM(31), UGREATER_FLAG)); in emit_single_op()
336 EMIT_SHIFT(SRA, SRAV); in emit_single_op()
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| D | sljitNativeMIPS_64.c | 407 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRA32, SRA) | T(dst) | DA(UGREATER_FLAG) | SH_IMM(31), UGRE… in emit_single_op()
431 EMIT_SHIFT(DSRA, DSRA32, SRA, DSRAV, SRAV); in emit_single_op()
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | shift-09.ll | 45 ; Check that we use SRAK over SRA where useful.
55 ; Check that we use SRA over SRAK where possible.
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| D | shift-03.ll | 5 ; Check the low end of the SRA range.
14 ; Check the high end of the defined SRA range.
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| D | shift-10.ll | 69 ; Test that SRA gets replaced with SRL if the sign bit is the only one
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| /external/llvm/test/CodeGen/X86/ |
| D | pr14204.ll | 4 ; SLL/SRA.
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 77 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; in PromoteIntegerResult()
628 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt); in PromoteIntRes_SRA()
867 case ISD::SRA: in PromoteIntegerOperand()
1316 case ISD::SRA: in ExpandIntegerResult()
1416 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
1418 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1421 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1423 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1427 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1435 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); in ExpandShiftByConstant()
[all …]
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| D | LegalizeVectorOps.cpp | 276 case ISD::SRA: in LegalizeOp()
589 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt); in ExpandLoad()
764 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand || in ExpandSEXTINREG()
777 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz); in ExpandSEXTINREG()
821 return DAG.getNode(ISD::SRA, DL, VT, in ExpandSIGN_EXTEND_VECTOR_INREG()
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| D | DAGCombiner.cpp | 1057 if (Opc == ISD::SRA) in PromoteIntShiftOp()
1328 case ISD::SRA: return visitSRA(N); in visit()
1421 case ISD::SRA: in combine()
2136 DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, in visitSDIV()
2149 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD, in visitSDIV() local
2155 return SRA; in visitSDIV()
2157 AddToWorklist(SRA.getNode()); in visitSDIV()
2158 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), SRA); in visitSDIV()
2336 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0, in visitMULHS()
2588 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && in SimplifyBinOpWithSameOpcodeHands()
[all …]
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| /external/valgrind/none/tests/mips64/ |
| D | shift_instructions.c | 10 SRA, SRAV, SRL, SRLV enumerator
177 case SRA: in main()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 95 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
98 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
192 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation()
756 case ISD::SRA: in LowerShifts()
757 return DAG.getNode(MSP430ISD::SRA, dl, in LowerShifts()
976 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); in LowerSETCC()
1155 case MSP430ISD::SRA: return "MSP430ISD::SRA"; in getTargetNodeName()
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| D | MSP430ISelLowering.h | 65 SHL, SRA, SRL enumerator
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| /external/v8/src/mips/ |
| D | constants-mips.cc | 226 case SRA: in InstructionType()
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| D | constants-mips.h | 375 SRA = ((0 << 3) + 3), enumerator
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| /external/v8/src/mips64/ |
| D | constants-mips64.cc | 230 case SRA: in InstructionType()
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| D | constants-mips64.h | 352 SRA = ((0 << 3) + 3), enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 323 SHL, SRA, SRL, ROTL, ROTR, enumerator
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| /external/llvm/lib/Target/R600/ |
| D | R600ISelLowering.cpp | 1051 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; in LowerSRXParts() local
1066 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); in LowerSRXParts()
1070 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); in LowerSRXParts()
1071 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero; in LowerSRXParts()
1573 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount); in LowerLOAD()
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| D | AMDGPUISelDAGToDAG.cpp | 548 case ISD::SRA: in Select()
1181 bool Signed = N->getOpcode() == ISD::SRA; in SelectS_BFEFromShifts()
1236 case ISD::SRA: in SelectS_BFE()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
512 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT)); in LowerSDIV24()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 820 case ISD::SRA: { in expandRxSBG()
830 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) { in expandRxSBG()
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