| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| D | Execution.cpp | 52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
55 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, in executeFAddInst() argument
66 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, in executeFSubInst() argument
77 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, in executeFMulInst() argument
88 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, in executeFDivInst() argument
99 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, in executeFRemInst() argument
103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
121 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 204 unsigned Src1 = 0, SubReg1; in isProfitableToTransform() local
222 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
223 if (Src1) in isProfitableToTransform()
227 if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform()
297 unsigned Src1 = 0, SubReg1; in transformInstruction() local
315 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1); in transformInstruction()
318 if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction()
319 assert(Src1 && "Can't delete copy w/o a valid original source!"); in transformInstruction()
331 if (!Src1) { in transformInstruction()
333 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
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| D | AArch64FastISel.cpp | 4496 const Value *Src1 = I->getOperand(1); in selectMul() local
4499 std::swap(Src0, Src1); in selectMul()
4502 if (const auto *C = dyn_cast<ConstantInt>(Src1)) in selectMul()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600ExpandSpecialInstrs.cpp | 98 unsigned Src1 = 0; in runOnMachineFunction() local
102 Src1 = MI.getOperand(2).getReg(); in runOnMachineFunction()
107 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
153 .addReg(Src1) in runOnMachineFunction()
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| D | R600Instructions.td | 805 // Src1 = Offset
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| /external/llvm/lib/Target/R600/ |
| D | R600ExpandSpecialInstrs.cpp | 225 unsigned Src1 = BMI->getOperand( in runOnMachineFunction() local
229 (void) Src1; in runOnMachineFunction()
231 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
276 unsigned Src1 = 0; in runOnMachineFunction() local
282 Src1 = MI.getOperand(Src1Idx).getReg(); in runOnMachineFunction()
288 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
293 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
328 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
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| D | SIShrinkInstructions.cpp | 100 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in canShrink() local
104 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0))) in canShrink()
257 const MachineOperand *Src1 = in runOnMachineFunction() local
259 if (Src1) in runOnMachineFunction()
260 Inst32.addOperand(*Src1); in runOnMachineFunction()
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| D | SIInstrInfo.cpp | 736 unsigned Src1 = MI->getOperand(2).getReg(); in expandPostRAPseudo() local
741 .addReg(RI.getSubReg(Src1, AMDGPU::sub0)) in expandPostRAPseudo()
745 .addReg(RI.getSubReg(Src1, AMDGPU::sub1)) in expandPostRAPseudo()
773 MachineOperand &Src1 = MI->getOperand(Src1Idx); in commuteInstruction() local
777 (!isOperandLegal(MI, Src0Idx, &Src1) || in commuteInstruction()
782 if (!Src1.isReg()) { in commuteInstruction()
784 if (NewMI || !Src1.isImm() || in commuteInstruction()
810 if (Src1.isImm()) in commuteInstruction()
811 Src0.ChangeToImmediate(Src1.getImm()); in commuteInstruction()
815 Src1.ChangeToRegister(Reg, false); in commuteInstruction()
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| D | R600InstrInfo.cpp | 1272 MachineOperand &Src1 = MI->getOperand( in buildSlotOfVectorInstruction() local
1275 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg()); in buildSlotOfVectorInstruction()
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| D | EvergreenInstructions.td | 268 // Src1 = Offset
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| D | SIInstrInfo.td | 798 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
800 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 159 SDValue Src1, SDValue Src2, uint64_t Size) { in emitCLC() argument
161 EVT PtrVT = Src1.getValueType(); in emitCLC()
171 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
174 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
193 SDValue Src1, SDValue Src2, SDValue Size, in EmitTargetCodeForMemcmp() argument
199 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); in EmitTargetCodeForMemcmp()
246 SDValue Src1, SDValue Src2, in EmitTargetCodeForStrcmp() argument
249 SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::Other, MVT::Glue); in EmitTargetCodeForStrcmp()
250 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, in EmitTargetCodeForStrcmp()
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| D | SystemZSelectionDAGInfo.h | 42 SDValue Src1, SDValue Src2, SDValue Size,
60 SDValue Src1, SDValue Src2,
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 158 MachineOperand &Src1 = MI->getOperand(1); in runOnMachineFunction() local
160 if (Src1.getImm() != 0) in runOnMachineFunction()
175 MachineOperand &Src1 = MI->getOperand(1); in runOnMachineFunction() local
180 unsigned SrcReg = Src1.getReg(); in runOnMachineFunction()
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| D | HexagonISelDAGToDAG.cpp | 1063 SDNode* Src1 = N->getOperand(0).getNode(); in SelectAdd() local
1064 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse() in SelectAdd()
1065 || Src1->getValueType(0) != MVT::i32) { in SelectAdd()
1073 Src1->getOperand(0), in SelectAdd()
1074 Src1->getOperand(1)); in SelectAdd()
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| /external/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 304 const MachineOperand &Src1 = MI->getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM() local
308 .addOperand(Src1) in processInstructionForSLM()
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| D | X86ISelLowering.cpp | 14734 SDValue Src1 = Op.getOperand(1); in LowerINTRINSIC_WO_CHAIN() local
14743 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2, in LowerINTRINSIC_WO_CHAIN()
14750 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2, in LowerINTRINSIC_WO_CHAIN()
14755 SDValue Src1 = Op.getOperand(1); in LowerINTRINSIC_WO_CHAIN() local
14769 Src1, Src2, Rnd), in LowerINTRINSIC_WO_CHAIN()
14774 Src1,Src2), in LowerINTRINSIC_WO_CHAIN()
14778 SDValue Src1 = Op.getOperand(1); in LowerINTRINSIC_WO_CHAIN() local
14792 Src1, Src2, Src3, Rnd), in LowerINTRINSIC_WO_CHAIN()
14793 Mask, Src1, Subtarget, DAG); in LowerINTRINSIC_WO_CHAIN()
14797 Src1, Src2, Src3), in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1016 unsigned Src1 = MI->getOperand(1).getReg(); in printArithExtend() local
1017 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) && in printArithExtend()
1019 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) && in printArithExtend()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 3120 SDValue Src1 = getValue(I.getOperand(0)); in visitShuffleVector() local
3129 EVT SrcVT = Src1.getValueType(); in visitShuffleVector()
3133 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, in visitShuffleVector()
3149 VT, Src1, Src2)); in visitShuffleVector()
3157 VT, Src2, Src1)); in visitShuffleVector()
3164 bool Src1U = Src1.getOpcode() == ISD::UNDEF; in visitShuffleVector()
3170 MOps1[0] = Src1; in visitShuffleVector()
3173 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
3187 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, in visitShuffleVector()
3243 SDValue &Src = Input == 0 ? Src1 : Src2; in visitShuffleVector()
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| D | LegalizeVectorTypes.cpp | 1359 SDValue Src1 = N->getOperand(2); in SplitVecOp_VSELECT() local
1375 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL); in SplitVecOp_VSELECT()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2678 SDValue Src1 = Op.getOperand(0); in LowerADDC_ADDE_SUBC_SUBE() local
2679 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); in LowerADDC_ADDE_SUBC_SUBE()
2680 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, in LowerADDC_ADDE_SUBC_SUBE()
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| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 6394 llvm::Value *Src1 = CGF.EmitScalarExpr(E->getArg(1)); in emitTernaryFPBuiltin() local
6398 return CGF.Builder.CreateCall3(F, Src0, Src1, Src2); in emitTernaryFPBuiltin()
6406 llvm::Value *Src1 = CGF.EmitScalarExpr(E->getArg(1)); in emitFPIntBuiltin() local
6409 return CGF.Builder.CreateCall2(F, Src0, Src1); in emitFPIntBuiltin()
6446 llvm::Value *Src1 = EmitScalarExpr(E->getArg(1)); in EmitR600BuiltinExpr() local
6453 return Builder.CreateCall4(F, Src0, Src1, Src2, Src3ToBool); in EmitR600BuiltinExpr()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 8793 unsigned Src1 = MI->getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
8808 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2); in EmitInstrWithCustomInserter()
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