| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-pic.ll | 61 ; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
62 ; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
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| /external/llvm/test/CodeGen/R600/ |
| D | pv.ll | 6 …eg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg …
28 %20 = extractelement <4 x float> %reg6, i32 0
29 %21 = extractelement <4 x float> %reg6, i32 1
30 %22 = extractelement <4 x float> %reg6, i32 2
31 %23 = extractelement <4 x float> %reg6, i32 3
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| D | big_alu.ll | 6 …eg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg …
46 %38 = extractelement <4 x float> %reg6, i32 0
47 %39 = extractelement <4 x float> %reg6, i32 1
48 %40 = extractelement <4 x float> %reg6, i32 2
49 %41 = extractelement <4 x float> %reg6, i32 3
|
| /external/elfutils/src/tests/ |
| D | run-varlocs.sh | 64 [40051c,40052b) {reg6}
|
| D | run-addrcfi.sh | 38 integer reg6 (%esi): same_value
85 integer reg6 (%esi): same_value
137 integer reg6 (%rbp): same_value
203 integer reg6 (%rbp): same_value
307 integer reg6 (r6): undefined
1334 integer reg6 (r6): undefined
2360 integer reg6 (%r6): same_value
2437 integer reg6 (%r6): same_value
2515 integer reg6 (r6): same_value
2591 integer reg6 (x6): undefined
|
| /external/skia/gm/ |
| D | glyph_pos.cpp | 194 static GMRegistry reg6(GlyphPosFillFactory);
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 221 const CPURegister& reg5, const CPURegister& reg6, in AreAliased() argument
229 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
258 const CPURegister& reg5, const CPURegister& reg6, in AreSameSizeAndType() argument
266 match &= !reg6.IsValid() || reg6.IsSameSizeAndType(reg1); in AreSameSizeAndType()
|
| D | assembler-arm64.h | 423 const CPURegister& reg6 = NoReg,
436 const CPURegister& reg6 = NoCPUReg,
|
| /external/v8/src/arm/ |
| D | macro-assembler-arm.cc | 3950 Register reg6) { in GetRegisterThatIsNotOneOf() argument
3957 if (reg6.is_valid()) regs |= reg6.bit(); in GetRegisterThatIsNotOneOf()
4001 Register reg6, in AreAliased() argument
4005 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
4014 if (reg6.is_valid()) regs |= reg6.bit(); in AreAliased()
|
| D | macro-assembler-arm.h | 53 Register reg6 = no_reg);
62 Register reg6 = no_reg,
|
| /external/llvm/include/llvm/Support/ |
| D | Dwarf.def | 201 HANDLE_DW_OP(0x56, reg6)
|
| /external/v8/src/mips/ |
| D | macro-assembler-mips.h | 85 Register reg6 = no_reg);
92 Register reg6 = no_reg,
|
| D | macro-assembler-mips.cc | 5952 Register reg6) { in GetRegisterThatIsNotOneOf() argument
5959 if (reg6.is_valid()) regs |= reg6.bit(); in GetRegisterThatIsNotOneOf()
6000 Register reg6, in AreAliased() argument
6004 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
6013 if (reg6.is_valid()) regs |= reg6.bit(); in AreAliased()
|
| /external/v8/src/mips64/ |
| D | macro-assembler-mips64.h | 91 Register reg6 = no_reg);
98 Register reg6 = no_reg,
|
| D | macro-assembler-mips64.cc | 5937 Register reg6) { in GetRegisterThatIsNotOneOf() argument
5944 if (reg6.is_valid()) regs |= reg6.bit(); in GetRegisterThatIsNotOneOf()
5985 Register reg6, in AreAliased() argument
5989 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
5998 if (reg6.is_valid()) regs |= reg6.bit(); in AreAliased()
|
| /external/v8/src/x87/ |
| D | macro-assembler-x87.cc | 2975 Register reg6, in AreAliased() argument
2979 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
2988 if (reg6.is_valid()) regs |= reg6.bit(); in AreAliased()
|
| D | macro-assembler-x87.h | 40 Register reg6 = no_reg,
|
| /external/v8/src/ia32/ |
| D | macro-assembler-ia32.cc | 3015 Register reg6, in AreAliased() argument
3019 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
3028 if (reg6.is_valid()) regs |= reg6.bit(); in AreAliased()
|
| D | macro-assembler-ia32.h | 40 Register reg6 = no_reg,
|
| /external/elfutils/src/libdw/ |
| D | known-dwarf.h | 523 ONE_KNOWN_DW_OP_DESC (reg6, DW_OP_reg6, "Register 6.") \
|
| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.cc | 5364 const CPURegister& reg5, const CPURegister& reg6, in AreAliased() argument
5372 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
5399 const CPURegister& reg5, const CPURegister& reg6, in AreSameSizeAndType() argument
5407 match &= !reg6.IsValid() || reg6.IsSameSizeAndType(reg1); in AreSameSizeAndType()
|
| D | assembler-a64.h | 412 const CPURegister& reg6 = NoReg,
426 const CPURegister& reg6 = NoCPUReg,
|
| /external/v8/src/x64/ |
| D | macro-assembler-x64.h | 60 Register reg6 = no_reg,
|
| D | macro-assembler-x64.cc | 4989 Register reg6, in AreAliased() argument
4993 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
5002 if (reg6.is_valid()) regs |= reg6.bit(); in AreAliased()
|