| /external/llvm/test/Transforms/ConstProp/ |
| D | 2008-07-07-VectorCompare.ll | 18 %foo = fcmp ueq <4 x float> <float 0.0, float 0.0, float 0.0, float
24 …%foo = fcmp ueq <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <float 1.0, float 1.0, f…
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| /external/llvm/test/Transforms/InstCombine/ |
| D | fcmp.ll | 218 %cmp = fcmp ueq double %call, 0.000000e+00
223 ; CHECK: fcmp ueq double %a, 0.000000e+00
228 %cmp = fcmp ueq double %call, 0.000000e+00
233 ; CHECK: fcmp ueq double %a, 0.000000e+00
239 %cmp = fcmp ueq double %call, 0.000000e+00
248 %cmp = fcmp ueq float %a, undef
269 %cmp = fcmp ueq float undef, undef
|
| D | cast-int-fcmp-eq-0.ll | 80 %cmp = fcmp ueq float %f, 0.0
86 ; CHECK: fcmp ueq
89 %cmp = fcmp ueq float %f, -0.0
98 %cmp = fcmp ueq float %f, 0.0
104 ; CHECK: fcmp ueq
107 %cmp = fcmp ueq float %f, -0.0
428 %cmp = fcmp ueq float %f, 0.5
436 %cmp = fcmp ueq float %f, 0.5
|
| D | or-fcmp.ll | 5 %a = fcmp ueq float %x, %y ; <i1> [#uses=1]
9 ; CHECK: fcmp ueq
|
| D | and-fcmp.ll | 4 %a = fcmp ueq float %x, %y
11 ; CHECK-NOT: fcmp ueq float %x, %y
|
| /external/llvm/test/CodeGen/Mips/ |
| D | fcmp.ll | 149 ; 32-C-DAG: c.ueq.s $f12, $f14
153 ; 64-C-DAG: c.ueq.s $f12, $f13
156 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
161 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
201 ; 32-C-DAG: c.ueq.s $f12, $f14
205 ; 64-C-DAG: c.ueq.s $f12, $f13
208 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
212 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
216 %1 = fcmp ueq float %a, %b
510 ; 32-C-DAG: c.ueq.d $f12, $f14
[all …]
|
| D | 2013-11-18-fp64-const0.ll | 22 %Cmp11 = fcmp ueq double 0xFDBD965CF1BB7FDA, undef
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | select.ll | 481 ; M2: c.ueq.s $f12, $f14
482 ; M3: c.ueq.s $f12, $f13
491 ; CMOV-32: c.ueq.s $f12, $f14
495 ; SEL-32: cmp.ueq.s $f0, $f12, $f14
501 ; CMOV-64: c.ueq.s $f12, $f13
505 ; SEL-64: cmp.ueq.s $f0, $f12, $f13
680 ; M2: c.ueq.d $f12, $f14
681 ; M3: c.ueq.d $f12, $f13
690 ; CMOV-32: c.ueq.d $f12, $f14
694 ; SEL-32: cmp.ueq.d $f0, $f12, $f14
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| D | valid-xfail-mips32.txt | 23 0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
|
| /external/llvm/test/MC/Mips/ |
| D | mips-fpu-instructions.s | 79 # CHECK: c.ueq.d $f12, $f14 # encoding: [0x33,0x60,0x2e,0x46]
80 # CHECK: c.ueq.s $f28, $f18 # encoding: [0x33,0xe0,0x12,0x46]
112 c.ueq.d $f12,$f14
113 c.ueq.s $f28,$f18
|
| /external/llvm/test/CodeGen/ARM/ |
| D | fpcmp_ueq.ll | 12 %tmp = fcmp ueq float %a,%b
|
| D | vfcmp.ll | 87 ; ueq is implemented with VCGT/VCGT/VORR/VMVN
96 %tmp3 = fcmp ueq <2 x float> %tmp1, %tmp2
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| D | valid-xfail-mips64r2.txt | 23 0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
45 0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| D | valid-xfail-mips64r5.txt | 23 0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
45 0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| D | valid-xfail-mips64r3.txt | 23 0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
45 0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| D | valid-xfail-mips4.txt | 23 0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| D | valid-mips64-xfail.txt | 23 0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
46 0x46 0xdd 0x29 0x33 # CHECK: c.ueq.ps $fcc1, $f5, $f29
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| D | valid-xfail-mips32r5.txt | 23 0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
45 0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| D | valid-xfail-mips32r3.txt | 23 0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
45 0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| D | valid-xfail-mips32r2.txt | 23 0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
45 0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-fast-isel-fcmp.ll | 113 %1 = fcmp ueq float %a, %b
160 %1 = fcmp ueq float %a, %a
|
| /external/llvm/test/CodeGen/R600/ |
| D | m0-spill.ll | 11 %cmp = fcmp ueq float 0.0, %4
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| D | llvm-stress-s2090927243-simplified.ll | 22 %Cmp32 = fcmp ueq float undef, 0x3CDA6E5E40000000
|
| /external/llvm/test/CodeGen/X86/ |
| D | sext-setcc-self.ll | 7 %0 = fcmp ueq <4 x float> %in, %in
|
| /external/llvm/test/Bitcode/ |
| D | miscInstructions.3.2.ll | 144 ; CHECK-NEXT: %res12 = fcmp ueq float %x1, %x2
145 %res12 = fcmp ueq float %x1, %x2
|