1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN:    -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN:    -check-prefix=ALL -check-prefix=CMOV \
5; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
6; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
7; RUN:    -check-prefix=ALL -check-prefix=CMOV \
8; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
9; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
10; RUN:    -check-prefix=ALL -check-prefix=CMOV \
11; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
12; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
13; RUN:    -check-prefix=ALL -check-prefix=CMOV \
14; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
15; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
16; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
17; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
18; RUN:    -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
19; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
20; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
21; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
22; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
23; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
24; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
25; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
26; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
27; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
28; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
29; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
30; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
31
32define signext i1 @tst_select_i1_i1(i1 signext %s,
33                                    i1 signext %x, i1 signext %y) {
34entry:
35  ; ALL-LABEL: tst_select_i1_i1:
36
37  ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
38  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
39  ; M2-M3:  nop
40  ; M2-M3:  move    $5, $6
41  ; M2-M3:  $[[BB0]]:
42  ; M2-M3:  jr      $ra
43  ; M2-M3:  move    $2, $5
44
45  ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
46  ; CMOV:   movn    $6, $5, $[[T0]]
47  ; CMOV:   move    $2, $6
48
49  ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
50  ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
51  ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
52  ; SEL:    or      $2, $[[T2]], $[[T1]]
53  %r = select i1 %s, i1 %x, i1 %y
54  ret i1 %r
55}
56
57define signext i8 @tst_select_i1_i8(i1 signext %s,
58                                    i8 signext %x, i8 signext %y) {
59entry:
60  ; ALL-LABEL: tst_select_i1_i8:
61
62  ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
63  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
64  ; M2-M3:  nop
65  ; M2-M3:  move    $5, $6
66  ; M2-M3:  $[[BB0]]:
67  ; M2-M3:  jr      $ra
68  ; M2-M3:  move    $2, $5
69
70  ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
71  ; CMOV:   movn    $6, $5, $[[T0]]
72  ; CMOV:   move    $2, $6
73
74  ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
75  ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
76  ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
77  ; SEL:    or      $2, $[[T2]], $[[T1]]
78  %r = select i1 %s, i8 %x, i8 %y
79  ret i8 %r
80}
81
82define signext i32 @tst_select_i1_i32(i1 signext %s,
83                                      i32 signext %x, i32 signext %y) {
84entry:
85  ; ALL-LABEL: tst_select_i1_i32:
86
87  ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
88  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
89  ; M2-M3:  nop
90  ; M2-M3:  move    $5, $6
91  ; M2-M3:  $[[BB0]]:
92  ; M2-M3:  jr      $ra
93  ; M2-M3:  move    $2, $5
94
95  ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
96  ; CMOV:   movn    $6, $5, $[[T0]]
97  ; CMOV:   move    $2, $6
98
99  ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
100  ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
101  ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
102  ; SEL:    or      $2, $[[T2]], $[[T1]]
103  %r = select i1 %s, i32 %x, i32 %y
104  ret i32 %r
105}
106
107define signext i64 @tst_select_i1_i64(i1 signext %s,
108                                      i64 signext %x, i64 signext %y) {
109entry:
110  ; ALL-LABEL: tst_select_i1_i64:
111
112  ; M2:     andi    $[[T0:[0-9]+]], $4, 1
113  ; M2:     bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
114  ; M2:     nop
115  ; M2:     lw      $[[T1:[0-9]+]], 16($sp)
116  ; M2:     $[[BB0]]:
117  ; FIXME: This branch is redundant
118  ; M2:     bnez    $[[T0]], $[[BB1:BB[0-9_]+]]
119  ; M2:     nop
120  ; M2:     lw      $[[T2:[0-9]+]], 20($sp)
121  ; M2:     $[[BB1]]:
122  ; M2:     move    $2, $[[T1]]
123  ; M2:     jr      $ra
124  ; M2:     move    $3, $[[T2]]
125
126  ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
127  ; CMOV-32:    lw      $2, 16($sp)
128  ; CMOV-32:    movn    $2, $6, $[[T0]]
129  ; CMOV-32:    lw      $3, 20($sp)
130  ; CMOV-32:    movn    $3, $7, $[[T0]]
131
132  ; SEL-32:     andi    $[[T0:[0-9]+]], $4, 1
133  ; SEL-32:     selnez  $[[T1:[0-9]+]], $6, $[[T0]]
134  ; SEL-32:     lw      $[[T2:[0-9]+]], 16($sp)
135  ; SEL-32:     seleqz  $[[T3:[0-9]+]], $[[T2]], $[[T0]]
136  ; SEL-32:     or      $2, $[[T1]], $[[T3]]
137  ; SEL-32:     selnez  $[[T4:[0-9]+]], $7, $[[T0]]
138  ; SEL-32:     lw      $[[T5:[0-9]+]], 20($sp)
139  ; SEL-32:     seleqz  $[[T6:[0-9]+]], $[[T5]], $[[T0]]
140  ; SEL-32:     or      $3, $[[T4]], $[[T6]]
141
142  ; M3:         andi    $[[T0:[0-9]+]], $4, 1
143  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
144  ; M3:         nop
145  ; M3:         move    $5, $6
146  ; M3:         $[[BB0]]:
147  ; M3:         jr      $ra
148  ; M3:         move    $2, $5
149
150  ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
151  ; CMOV-64:    movn    $6, $5, $[[T0]]
152  ; CMOV-64:    move    $2, $6
153
154  ; SEL-64:     andi    $[[T0:[0-9]+]], $4, 1
155  ; FIXME: This shift is redundant
156  ; SEL-64:     sll     $[[T0]], $[[T0]], 0
157  ; SEL-64:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
158  ; SEL-64:     selnez  $[[T0]], $5, $[[T0]]
159  ; SEL-64:     or      $2, $[[T0]], $[[T1]]
160  %r = select i1 %s, i64 %x, i64 %y
161  ret i64 %r
162}
163
164define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
165entry:
166  ; ALL-LABEL: tst_select_i1_float:
167
168  ; M2-M3:      andi    $[[T0:[0-9]+]], $4, 1
169  ; M2-M3:      bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
170  ; M2-M3:      nop
171  ; M2:         jr      $ra
172  ; M2:         mtc1    $6, $f0
173  ; M3:         mov.s   $f13, $f14
174  ; M2-M3:      $[[BB0]]:
175  ; M2-M3:      jr      $ra
176  ; M2:         mtc1    $5, $f0
177  ; M3:         mov.s   $f0, $f13
178
179  ; CMOV-32:    mtc1    $6, $f0
180  ; CMOV-32:    mtc1    $5, $f1
181  ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
182  ; CMOV-32:    movn.s  $f0, $f1, $[[T0]]
183
184  ; SEL-32:     mtc1    $5, $[[F0:f[0-9]+]]
185  ; SEL-32:     mtc1    $6, $[[F1:f[0-9]+]]
186  ; SEL-32:     mtc1    $4, $f0
187  ; SEL-32:     sel.s   $f0, $[[F1]], $[[F0]]
188
189  ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
190  ; CMOV-64:    movn.s  $f14, $f13, $[[T0]]
191  ; CMOV-64:    mov.s   $f0, $f14
192
193  ; SEL-64:     mtc1    $4, $f0
194  ; SEL-64:     sel.s   $f0, $f14, $f13
195  %r = select i1 %s, float %x, float %y
196  ret float %r
197}
198
199define float @tst_select_i1_float_reordered(float %x, float %y,
200                                            i1 signext %s) {
201entry:
202  ; ALL-LABEL: tst_select_i1_float_reordered:
203
204  ; M2-M3:      andi    $[[T0:[0-9]+]], $6, 1
205  ; M2-M3:      bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
206  ; M2-M3:      nop
207  ; M2:         mov.s   $f12, $f14
208  ; M3:         mov.s   $f12, $f13
209  ; M2-M3:      $[[BB0]]:
210  ; M2-M3:      jr      $ra
211  ; M2-M3:      mov.s   $f0, $f12
212
213  ; CMOV-32:    andi    $[[T0:[0-9]+]], $6, 1
214  ; CMOV-32:    movn.s  $f14, $f12, $[[T0]]
215  ; CMOV-32:    mov.s   $f0, $f14
216
217  ; SEL-32:     mtc1    $6, $f0
218  ; SEL-32:     sel.s   $f0, $f14, $f12
219
220  ; CMOV-64:    andi    $[[T0:[0-9]+]], $6, 1
221  ; CMOV-64:    movn.s  $f13, $f12, $[[T0]]
222  ; CMOV-64:    mov.s   $f0, $f13
223
224  ; SEL-64:     mtc1    $6, $f0
225  ; SEL-64:     sel.s   $f0, $f13, $f12
226  %r = select i1 %s, float %x, float %y
227  ret float %r
228}
229
230define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
231entry:
232  ; ALL-LABEL: tst_select_i1_double:
233
234  ; M2:         andi    $[[T0:[0-9]+]], $4, 1
235  ; M2:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
236  ; M2:         nop
237  ; M2:         ldc1    $f0, 16($sp)
238  ; M2:         jr      $ra
239  ; M2:         nop
240  ; M2:         $[[BB0]]:
241  ; M2:         mtc1    $7, $f0
242  ; M2:         jr      $ra
243  ; M2:         mtc1    $6, $f1
244
245  ; CMOV-32:      mtc1    $7, $[[F0:f[0-9]+]]
246  ; CMOV-32R1:    mtc1    $6, $f{{[0-9]+}}
247  ; CMOV-32R2-R5: mthc1   $6, $[[F0]]
248  ; CMOV-32:      andi    $[[T0:[0-9]+]], $4, 1
249  ; CMOV-32:      ldc1    $f0, 16($sp)
250  ; CMOV-32:      movn.d  $f0, $[[F0]], $[[T0]]
251
252  ; SEL-32:     mtc1    $7, $[[F0:f[0-9]+]]
253  ; SEL-32:     mthc1   $6, $[[F0]]
254  ; SEL-32:     ldc1    $[[F1:f[0-9]+]], 16($sp)
255  ; SEL-32:     mtc1    $4, $f0
256  ; SEL-32:     sel.d   $f0, $[[F1]], $[[F0]]
257
258  ; M3:         andi    $[[T0:[0-9]+]], $4, 1
259  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
260  ; M3:         nop
261  ; M3:         mov.d   $f13, $f14
262  ; M3:         $[[BB0]]:
263  ; M3:         jr      $ra
264  ; M3:         mov.d   $f0, $f13
265
266  ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
267  ; CMOV-64:    movn.d  $f14, $f13, $[[T0]]
268  ; CMOV-64:    mov.d   $f0, $f14
269
270  ; SEL-64:     mtc1    $4, $f0
271  ; SEL-64:     sel.d   $f0, $f14, $f13
272  %r = select i1 %s, double %x, double %y
273  ret double %r
274}
275
276define double @tst_select_i1_double_reordered(double %x, double %y,
277                                              i1 signext %s) {
278entry:
279  ; ALL-LABEL: tst_select_i1_double_reordered:
280
281  ; M2:         lw      $[[T0:[0-9]+]], 16($sp)
282  ; M2:         andi    $[[T1:[0-9]+]], $[[T0]], 1
283  ; M2:         bnez    $[[T1]], $[[BB0:BB[0-9_]+]]
284  ; M2:         nop
285  ; M2:         mov.d   $f12, $f14
286  ; M2:         $[[BB0]]:
287  ; M2:         jr      $ra
288  ; M2:         mov.d   $f0, $f12
289
290  ; CMOV-32:    lw      $[[T0:[0-9]+]], 16($sp)
291  ; CMOV-32:    andi    $[[T1:[0-9]+]], $[[T0]], 1
292  ; CMOV-32:    movn.d  $f14, $f12, $[[T1]]
293  ; CMOV-32:    mov.d   $f0, $f14
294
295  ; SEL-32:     lw      $[[T0:[0-9]+]], 16($sp)
296  ; SEL-32:     mtc1    $[[T0]], $f0
297  ; SEL-32:     sel.d   $f0, $f14, $f12
298
299  ; M3:         andi    $[[T0:[0-9]+]], $6, 1
300  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
301  ; M3:         nop
302  ; M3:         mov.d   $f12, $f13
303  ; M3:         $[[BB0]]:
304  ; M3:         jr      $ra
305  ; M3:         mov.d   $f0, $f12
306
307  ; CMOV-64:    andi    $[[T0:[0-9]+]], $6, 1
308  ; CMOV-64:    movn.d  $f13, $f12, $[[T0]]
309  ; CMOV-64:    mov.d   $f0, $f13
310
311  ; SEL-64:     mtc1    $6, $f0
312  ; SEL-64:     sel.d   $f0, $f13, $f12
313  %r = select i1 %s, double %x, double %y
314  ret double %r
315}
316
317define float @tst_select_fcmp_olt_float(float %x, float %y) {
318entry:
319  ; ALL-LABEL: tst_select_fcmp_olt_float:
320
321  ; M2:         c.olt.s   $f12, $f14
322  ; M3:         c.olt.s   $f12, $f13
323  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
324  ; M2-M3:      nop
325  ; M2:         mov.s     $f12, $f14
326  ; M3:         mov.s     $f12, $f13
327  ; M2-M3:      $[[BB0]]:
328  ; M2-M3:      jr        $ra
329  ; M2-M3:      mov.s     $f0, $f12
330
331  ; CMOV-32:    c.olt.s   $f12, $f14
332  ; CMOV-32:    movt.s    $f14, $f12, $fcc0
333  ; CMOV-32:    mov.s     $f0, $f14
334
335  ; SEL-32:     cmp.lt.s  $f0, $f12, $f14
336  ; SEL-32:     sel.s     $f0, $f14, $f12
337
338  ; CMOV-64:    c.olt.s   $f12, $f13
339  ; CMOV-64:    movt.s    $f13, $f12, $fcc0
340  ; CMOV-64:    mov.s     $f0, $f13
341
342  ; SEL-64:     cmp.lt.s  $f0, $f12, $f13
343  ; SEL-64:     sel.s     $f0, $f13, $f12
344  %s = fcmp olt float %x, %y
345  %r = select i1 %s, float %x, float %y
346  ret float %r
347}
348
349define float @tst_select_fcmp_ole_float(float %x, float %y) {
350entry:
351  ; ALL-LABEL: tst_select_fcmp_ole_float:
352
353  ; M2:         c.ole.s   $f12, $f14
354  ; M3:         c.ole.s   $f12, $f13
355  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
356  ; M2-M3:      nop
357  ; M2:         mov.s     $f12, $f14
358  ; M3:         mov.s     $f12, $f13
359  ; M2-M3:      $[[BB0]]:
360  ; M2-M3:      jr        $ra
361  ; M2-M3:      mov.s     $f0, $f12
362
363  ; CMOV-32:    c.ole.s   $f12, $f14
364  ; CMOV-32:    movt.s    $f14, $f12, $fcc0
365  ; CMOV-32:    mov.s     $f0, $f14
366
367  ; SEL-32:     cmp.le.s  $f0, $f12, $f14
368  ; SEL-32:     sel.s     $f0, $f14, $f12
369
370  ; CMOV-64:    c.ole.s   $f12, $f13
371  ; CMOV-64:    movt.s    $f13, $f12, $fcc0
372  ; CMOV-64:    mov.s     $f0, $f13
373
374  ; SEL-64:     cmp.le.s  $f0, $f12, $f13
375  ; SEL-64:     sel.s     $f0, $f13, $f12
376  %s = fcmp ole float %x, %y
377  %r = select i1 %s, float %x, float %y
378  ret float %r
379}
380
381define float @tst_select_fcmp_ogt_float(float %x, float %y) {
382entry:
383  ; ALL-LABEL: tst_select_fcmp_ogt_float:
384
385  ; M2:         c.ule.s   $f12, $f14
386  ; M3:         c.ule.s   $f12, $f13
387  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
388  ; M2-M3:      nop
389  ; M2:         mov.s     $f12, $f14
390  ; M3:         mov.s     $f12, $f13
391  ; M2-M3:      $[[BB0]]:
392  ; M2-M3:      jr        $ra
393  ; M2-M3:      mov.s     $f0, $f12
394
395  ; CMOV-32:    c.ule.s   $f12, $f14
396  ; CMOV-32:    movf.s    $f14, $f12, $fcc0
397  ; CMOV-32:    mov.s     $f0, $f14
398
399  ; SEL-32:     cmp.lt.s  $f0, $f14, $f12
400  ; SEL-32:     sel.s     $f0, $f14, $f12
401
402  ; CMOV-64:    c.ule.s   $f12, $f13
403  ; CMOV-64:    movf.s    $f13, $f12, $fcc0
404  ; CMOV-64:    mov.s     $f0, $f13
405
406  ; SEL-64:     cmp.lt.s  $f0, $f13, $f12
407  ; SEL-64:     sel.s     $f0, $f13, $f12
408  %s = fcmp ogt float %x, %y
409  %r = select i1 %s, float %x, float %y
410  ret float %r
411}
412
413define float @tst_select_fcmp_oge_float(float %x, float %y) {
414entry:
415  ; ALL-LABEL: tst_select_fcmp_oge_float:
416
417  ; M2:         c.ult.s   $f12, $f14
418  ; M3:         c.ult.s   $f12, $f13
419  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
420  ; M2-M3:      nop
421  ; M2:         mov.s     $f12, $f14
422  ; M3:         mov.s     $f12, $f13
423  ; M2-M3:      $[[BB0]]:
424  ; M2-M3:      jr        $ra
425  ; M2-M3:      mov.s     $f0, $f12
426
427  ; CMOV-32:    c.ult.s   $f12, $f14
428  ; CMOV-32:    movf.s    $f14, $f12, $fcc0
429  ; CMOV-32:    mov.s     $f0, $f14
430
431  ; SEL-32:     cmp.le.s  $f0, $f14, $f12
432  ; SEL-32:     sel.s     $f0, $f14, $f12
433
434  ; CMOV-64:    c.ult.s   $f12, $f13
435  ; CMOV-64:    movf.s    $f13, $f12, $fcc0
436  ; CMOV-64:    mov.s     $f0, $f13
437
438  ; SEL-64:     cmp.le.s  $f0, $f13, $f12
439  ; SEL-64:     sel.s     $f0, $f13, $f12
440  %s = fcmp oge float %x, %y
441  %r = select i1 %s, float %x, float %y
442  ret float %r
443}
444
445define float @tst_select_fcmp_oeq_float(float %x, float %y) {
446entry:
447  ; ALL-LABEL: tst_select_fcmp_oeq_float:
448
449  ; M2:         c.eq.s    $f12, $f14
450  ; M3:         c.eq.s    $f12, $f13
451  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
452  ; M2-M3:      nop
453  ; M2:         mov.s     $f12, $f14
454  ; M3:         mov.s     $f12, $f13
455  ; M2-M3:      $[[BB0]]:
456  ; M2-M3:      jr        $ra
457  ; M2-M3:      mov.s     $f0, $f12
458
459  ; CMOV-32:    c.eq.s    $f12, $f14
460  ; CMOV-32:    movt.s    $f14, $f12, $fcc0
461  ; CMOV-32:    mov.s     $f0, $f14
462
463  ; SEL-32:     cmp.eq.s  $f0, $f12, $f14
464  ; SEL-32:     sel.s     $f0, $f14, $f12
465
466  ; CMOV-64:    c.eq.s    $f12, $f13
467  ; CMOV-64:    movt.s    $f13, $f12, $fcc0
468  ; CMOV-64:    mov.s     $f0, $f13
469
470  ; SEL-64:     cmp.eq.s  $f0, $f12, $f13
471  ; SEL-64:     sel.s     $f0, $f13, $f12
472  %s = fcmp oeq float %x, %y
473  %r = select i1 %s, float %x, float %y
474  ret float %r
475}
476
477define float @tst_select_fcmp_one_float(float %x, float %y) {
478entry:
479  ; ALL-LABEL: tst_select_fcmp_one_float:
480
481  ; M2:         c.ueq.s   $f12, $f14
482  ; M3:         c.ueq.s   $f12, $f13
483  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
484  ; M2-M3:      nop
485  ; M2:         mov.s     $f12, $f14
486  ; M3:         mov.s     $f12, $f13
487  ; M2-M3:      $[[BB0]]:
488  ; M2-M3:      jr        $ra
489  ; M2-M3:      mov.s     $f0, $f12
490
491  ; CMOV-32:    c.ueq.s   $f12, $f14
492  ; CMOV-32:    movf.s    $f14, $f12, $fcc0
493  ; CMOV-32:    mov.s     $f0, $f14
494
495  ; SEL-32:     cmp.ueq.s $f0, $f12, $f14
496  ; SEL-32:     mfc1      $[[T0:[0-9]+]], $f0
497  ; SEL-32:     not       $[[T0]], $[[T0]]
498  ; SEL-32:     mtc1      $[[T0:[0-9]+]], $f0
499  ; SEL-32:     sel.s     $f0, $f14, $f12
500
501  ; CMOV-64:    c.ueq.s   $f12, $f13
502  ; CMOV-64:    movf.s    $f13, $f12, $fcc0
503  ; CMOV-64:    mov.s     $f0, $f13
504
505  ; SEL-64:     cmp.ueq.s $f0, $f12, $f13
506  ; SEL-64:     mfc1      $[[T0:[0-9]+]], $f0
507  ; SEL-64:     not       $[[T0]], $[[T0]]
508  ; SEL-64:     mtc1      $[[T0:[0-9]+]], $f0
509  ; SEL-64:     sel.s     $f0, $f13, $f12
510
511  %s = fcmp one float %x, %y
512  %r = select i1 %s, float %x, float %y
513  ret float %r
514}
515
516define double @tst_select_fcmp_olt_double(double %x, double %y) {
517entry:
518  ; ALL-LABEL: tst_select_fcmp_olt_double:
519
520  ; M2:         c.olt.d   $f12, $f14
521  ; M3:         c.olt.d   $f12, $f13
522  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
523  ; M2-M3:      nop
524  ; M2:         mov.d     $f12, $f14
525  ; M3:         mov.d     $f12, $f13
526  ; M2-M3:      $[[BB0]]:
527  ; M2-M3:      jr        $ra
528  ; M2-M3:      mov.d     $f0, $f12
529
530  ; CMOV-32:    c.olt.d   $f12, $f14
531  ; CMOV-32:    movt.d    $f14, $f12, $fcc0
532  ; CMOV-32:    mov.d     $f0, $f14
533
534  ; SEL-32:     cmp.lt.d  $f0, $f12, $f14
535  ; SEL-32:     sel.d     $f0, $f14, $f12
536
537  ; CMOV-64:    c.olt.d   $f12, $f13
538  ; CMOV-64:    movt.d    $f13, $f12, $fcc0
539  ; CMOV-64:    mov.d     $f0, $f13
540
541  ; SEL-64:     cmp.lt.d  $f0, $f12, $f13
542  ; SEL-64:     sel.d     $f0, $f13, $f12
543  %s = fcmp olt double %x, %y
544  %r = select i1 %s, double %x, double %y
545  ret double %r
546}
547
548define double @tst_select_fcmp_ole_double(double %x, double %y) {
549entry:
550  ; ALL-LABEL: tst_select_fcmp_ole_double:
551
552  ; M2:         c.ole.d   $f12, $f14
553  ; M3:         c.ole.d   $f12, $f13
554  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
555  ; M2-M3:      nop
556  ; M2:         mov.d     $f12, $f14
557  ; M3:         mov.d     $f12, $f13
558  ; M2-M3:      $[[BB0]]:
559  ; M2-M3:      jr        $ra
560  ; M2-M3:      mov.d     $f0, $f12
561
562  ; CMOV-32:    c.ole.d   $f12, $f14
563  ; CMOV-32:    movt.d    $f14, $f12, $fcc0
564  ; CMOV-32:    mov.d     $f0, $f14
565
566  ; SEL-32:     cmp.le.d  $f0, $f12, $f14
567  ; SEL-32:     sel.d     $f0, $f14, $f12
568
569  ; CMOV-64:    c.ole.d   $f12, $f13
570  ; CMOV-64:    movt.d    $f13, $f12, $fcc0
571  ; CMOV-64:    mov.d     $f0, $f13
572
573  ; SEL-64:     cmp.le.d  $f0, $f12, $f13
574  ; SEL-64:     sel.d     $f0, $f13, $f12
575  %s = fcmp ole double %x, %y
576  %r = select i1 %s, double %x, double %y
577  ret double %r
578}
579
580define double @tst_select_fcmp_ogt_double(double %x, double %y) {
581entry:
582  ; ALL-LABEL: tst_select_fcmp_ogt_double:
583
584  ; M2:         c.ule.d   $f12, $f14
585  ; M3:         c.ule.d   $f12, $f13
586  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
587  ; M2-M3:      nop
588  ; M2:         mov.d     $f12, $f14
589  ; M3:         mov.d     $f12, $f13
590  ; M2-M3:      $[[BB0]]:
591  ; M2-M3:      jr        $ra
592  ; M2-M3:      mov.d     $f0, $f12
593
594  ; CMOV-32:    c.ule.d   $f12, $f14
595  ; CMOV-32:    movf.d    $f14, $f12, $fcc0
596  ; CMOV-32:    mov.d     $f0, $f14
597
598  ; SEL-32:     cmp.lt.d  $f0, $f14, $f12
599  ; SEL-32:     sel.d     $f0, $f14, $f12
600
601  ; CMOV-64:    c.ule.d   $f12, $f13
602  ; CMOV-64:    movf.d    $f13, $f12, $fcc0
603  ; CMOV-64:    mov.d     $f0, $f13
604
605  ; SEL-64:     cmp.lt.d  $f0, $f13, $f12
606  ; SEL-64:     sel.d     $f0, $f13, $f12
607  %s = fcmp ogt double %x, %y
608  %r = select i1 %s, double %x, double %y
609  ret double %r
610}
611
612define double @tst_select_fcmp_oge_double(double %x, double %y) {
613entry:
614  ; ALL-LABEL: tst_select_fcmp_oge_double:
615
616  ; M2:         c.ult.d   $f12, $f14
617  ; M3:         c.ult.d   $f12, $f13
618  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
619  ; M2-M3:      nop
620  ; M2:         mov.d     $f12, $f14
621  ; M3:         mov.d     $f12, $f13
622  ; M2-M3:      $[[BB0]]:
623  ; M2-M3:      jr        $ra
624  ; M2-M3:      mov.d     $f0, $f12
625
626  ; CMOV-32:    c.ult.d   $f12, $f14
627  ; CMOV-32:    movf.d    $f14, $f12, $fcc0
628  ; CMOV-32:    mov.d     $f0, $f14
629
630  ; SEL-32:     cmp.le.d  $f0, $f14, $f12
631  ; SEL-32:     sel.d     $f0, $f14, $f12
632
633  ; CMOV-64:    c.ult.d   $f12, $f13
634  ; CMOV-64:    movf.d    $f13, $f12, $fcc0
635  ; CMOV-64:    mov.d     $f0, $f13
636
637  ; SEL-64:     cmp.le.d  $f0, $f13, $f12
638  ; SEL-64:     sel.d     $f0, $f13, $f12
639  %s = fcmp oge double %x, %y
640  %r = select i1 %s, double %x, double %y
641  ret double %r
642}
643
644define double @tst_select_fcmp_oeq_double(double %x, double %y) {
645entry:
646  ; ALL-LABEL: tst_select_fcmp_oeq_double:
647
648  ; M2:         c.eq.d    $f12, $f14
649  ; M3:         c.eq.d    $f12, $f13
650  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
651  ; M2-M3:      nop
652  ; M2:         mov.d     $f12, $f14
653  ; M3:         mov.d     $f12, $f13
654  ; M2-M3:      $[[BB0]]:
655  ; M2-M3:      jr        $ra
656  ; M2-M3:      mov.d     $f0, $f12
657
658  ; CMOV-32:    c.eq.d    $f12, $f14
659  ; CMOV-32:    movt.d    $f14, $f12, $fcc0
660  ; CMOV-32:    mov.d     $f0, $f14
661
662  ; SEL-32:     cmp.eq.d  $f0, $f12, $f14
663  ; SEL-32:     sel.d     $f0, $f14, $f12
664
665  ; CMOV-64:    c.eq.d    $f12, $f13
666  ; CMOV-64:    movt.d    $f13, $f12, $fcc0
667  ; CMOV-64:    mov.d     $f0, $f13
668
669  ; SEL-64:     cmp.eq.d  $f0, $f12, $f13
670  ; SEL-64:     sel.d     $f0, $f13, $f12
671  %s = fcmp oeq double %x, %y
672  %r = select i1 %s, double %x, double %y
673  ret double %r
674}
675
676define double @tst_select_fcmp_one_double(double %x, double %y) {
677entry:
678  ; ALL-LABEL: tst_select_fcmp_one_double:
679
680  ; M2:         c.ueq.d   $f12, $f14
681  ; M3:         c.ueq.d   $f12, $f13
682  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
683  ; M2-M3:      nop
684  ; M2:         mov.d     $f12, $f14
685  ; M3:         mov.d     $f12, $f13
686  ; M2-M3:      $[[BB0]]:
687  ; M2-M3:      jr        $ra
688  ; M2-M3:      mov.d     $f0, $f12
689
690  ; CMOV-32:    c.ueq.d   $f12, $f14
691  ; CMOV-32:    movf.d    $f14, $f12, $fcc0
692  ; CMOV-32:    mov.d     $f0, $f14
693
694  ; SEL-32:     cmp.ueq.d $f0, $f12, $f14
695  ; SEL-32:     mfc1      $[[T0:[0-9]+]], $f0
696  ; SEL-32:     not       $[[T0]], $[[T0]]
697  ; SEL-32:     mtc1      $[[T0:[0-9]+]], $f0
698  ; SEL-32:     sel.d     $f0, $f14, $f12
699
700  ; CMOV-64:    c.ueq.d   $f12, $f13
701  ; CMOV-64:    movf.d    $f13, $f12, $fcc0
702  ; CMOV-64:    mov.d     $f0, $f13
703
704  ; SEL-64:     cmp.ueq.d $f0, $f12, $f13
705  ; SEL-64:     mfc1      $[[T0:[0-9]+]], $f0
706  ; SEL-64:     not       $[[T0]], $[[T0]]
707  ; SEL-64:     mtc1      $[[T0:[0-9]+]], $f0
708  ; SEL-64:     sel.d     $f0, $f13, $f12
709  %s = fcmp one double %x, %y
710  %r = select i1 %s, double %x, double %y
711  ret double %r
712}
713