1 /*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "disassembler_arm64.h"
18
19 #include <inttypes.h>
20
21 #include <sstream>
22
23 #include "base/logging.h"
24 #include "base/stringprintf.h"
25 #include "thread.h"
26
27 namespace art {
28 namespace arm64 {
29
30 // This enumeration should mirror the declarations in
31 // runtime/arch/arm64/registers_arm64.h. We do not include that file to
32 // avoid a dependency on libart.
33 enum {
34 TR = 18,
35 ETR = 21,
36 IP0 = 16,
37 IP1 = 17,
38 FP = 29,
39 LR = 30
40 };
41
AppendRegisterNameToOutput(const vixl::Instruction * instr,const vixl::CPURegister & reg)42 void CustomDisassembler::AppendRegisterNameToOutput(
43 const vixl::Instruction* instr,
44 const vixl::CPURegister& reg) {
45 USE(instr);
46 if (reg.IsRegister() && reg.Is64Bits()) {
47 if (reg.code() == TR) {
48 AppendToOutput("tr");
49 return;
50 } else if (reg.code() == LR) {
51 AppendToOutput("lr");
52 return;
53 }
54 // Fall through.
55 }
56 // Print other register names as usual.
57 Disassembler::AppendRegisterNameToOutput(instr, reg);
58 }
59
VisitLoadLiteral(const vixl::Instruction * instr)60 void CustomDisassembler::VisitLoadLiteral(const vixl::Instruction* instr) {
61 Disassembler::VisitLoadLiteral(instr);
62
63 if (!read_literals_) {
64 return;
65 }
66
67 void* data_address = instr->LiteralAddress<void*>();
68 vixl::Instr op = instr->Mask(vixl::LoadLiteralMask);
69
70 switch (op) {
71 case vixl::LDR_w_lit:
72 case vixl::LDR_x_lit:
73 case vixl::LDRSW_x_lit: {
74 int64_t data = op == vixl::LDR_x_lit ? *reinterpret_cast<int64_t*>(data_address)
75 : *reinterpret_cast<int32_t*>(data_address);
76 AppendToOutput(" (0x%" PRIx64 " / %" PRId64 ")", data, data);
77 break;
78 }
79 case vixl::LDR_s_lit:
80 case vixl::LDR_d_lit: {
81 double data = (op == vixl::LDR_s_lit) ? *reinterpret_cast<float*>(data_address)
82 : *reinterpret_cast<double*>(data_address);
83 AppendToOutput(" (%g)", data);
84 break;
85 }
86 default:
87 break;
88 }
89 }
90
VisitLoadStoreUnsignedOffset(const vixl::Instruction * instr)91 void CustomDisassembler::VisitLoadStoreUnsignedOffset(const vixl::Instruction* instr) {
92 Disassembler::VisitLoadStoreUnsignedOffset(instr);
93
94 if (instr->Rn() == TR) {
95 int64_t offset = instr->ImmLSUnsigned() << instr->SizeLS();
96 std::ostringstream tmp_stream;
97 Thread::DumpThreadOffset<8>(tmp_stream, static_cast<uint32_t>(offset));
98 AppendToOutput(" (%s)", tmp_stream.str().c_str());
99 }
100 }
101
Dump(std::ostream & os,const uint8_t * begin)102 size_t DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin) {
103 const vixl::Instruction* instr = reinterpret_cast<const vixl::Instruction*>(begin);
104 decoder.Decode(instr);
105 os << FormatInstructionPointer(begin)
106 << StringPrintf(": %08x\t%s\n", instr->InstructionBits(), disasm.GetOutput());
107 return vixl::kInstructionSize;
108 }
109
Dump(std::ostream & os,const uint8_t * begin,const uint8_t * end)110 void DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) {
111 for (const uint8_t* cur = begin; cur < end; cur += vixl::kInstructionSize) {
112 Dump(os, cur);
113 }
114 }
115
116 } // namespace arm64
117 } // namespace art
118