1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include <algorithm>
31 #include <memory>
32 using namespace clang;
33
34 //===----------------------------------------------------------------------===//
35 // Common code shared among targets.
36 //===----------------------------------------------------------------------===//
37
38 /// DefineStd - Define a macro name and standard variants. For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40 /// when in GNU mode.
DefineStd(MacroBuilder & Builder,StringRef MacroName,const LangOptions & Opts)41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42 const LangOptions &Opts) {
43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46 // in the user's namespace.
47 if (Opts.GNUMode)
48 Builder.defineMacro(MacroName);
49
50 // Define __unix.
51 Builder.defineMacro("__" + MacroName);
52
53 // Define __unix__.
54 Builder.defineMacro("__" + MacroName + "__");
55 }
56
defineCPUMacros(MacroBuilder & Builder,StringRef CPUName,bool Tuning=true)57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58 bool Tuning = true) {
59 Builder.defineMacro("__" + CPUName);
60 Builder.defineMacro("__" + CPUName + "__");
61 if (Tuning)
62 Builder.defineMacro("__tune_" + CPUName + "__");
63 }
64
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
68
69 namespace {
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
72 protected:
73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74 MacroBuilder &Builder) const=0;
75 public:
OSTargetInfo(const llvm::Triple & Triple)76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const77 void getTargetDefines(const LangOptions &Opts,
78 MacroBuilder &Builder) const override {
79 TgtInfo::getTargetDefines(Opts, Builder);
80 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81 }
82
83 };
84 } // end anonymous namespace
85
86
getDarwinDefines(MacroBuilder & Builder,const LangOptions & Opts,const llvm::Triple & Triple,StringRef & PlatformName,VersionTuple & PlatformMinVersion)87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88 const llvm::Triple &Triple,
89 StringRef &PlatformName,
90 VersionTuple &PlatformMinVersion) {
91 Builder.defineMacro("__APPLE_CC__", "6000");
92 Builder.defineMacro("__APPLE__");
93 Builder.defineMacro("OBJC_NEW_PROPERTIES");
94 // AddressSanitizer doesn't play well with source fortification, which is on
95 // by default on Darwin.
96 if (Opts.Sanitize.has(SanitizerKind::Address))
97 Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99 if (!Opts.ObjCAutoRefCount) {
100 // __weak is always defined, for use in blocks and with objc pointers.
101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103 // Darwin defines __strong even in C mode (just to nothing).
104 if (Opts.getGC() != LangOptions::NonGC)
105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106 else
107 Builder.defineMacro("__strong", "");
108
109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110 // allow this in C, since one might have block pointers in structs that
111 // are used in pure C code and in Objective-C ARC.
112 Builder.defineMacro("__unsafe_unretained", "");
113 }
114
115 if (Opts.Static)
116 Builder.defineMacro("__STATIC__");
117 else
118 Builder.defineMacro("__DYNAMIC__");
119
120 if (Opts.POSIXThreads)
121 Builder.defineMacro("_REENTRANT");
122
123 // Get the platform type and version number from the triple.
124 unsigned Maj, Min, Rev;
125 if (Triple.isMacOSX()) {
126 Triple.getMacOSXVersion(Maj, Min, Rev);
127 PlatformName = "macosx";
128 } else {
129 Triple.getOSVersion(Maj, Min, Rev);
130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131 }
132
133 // If -target arch-pc-win32-macho option specified, we're
134 // generating code for Win32 ABI. No need to emit
135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136 if (PlatformName == "win32") {
137 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138 return;
139 }
140
141 // Set the appropriate OS version define.
142 if (Triple.isiOS()) {
143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144 char Str[6];
145 Str[0] = '0' + Maj;
146 Str[1] = '0' + (Min / 10);
147 Str[2] = '0' + (Min % 10);
148 Str[3] = '0' + (Rev / 10);
149 Str[4] = '0' + (Rev % 10);
150 Str[5] = '\0';
151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
152 Str);
153 } else if (Triple.isMacOSX()) {
154 // Note that the Driver allows versions which aren't representable in the
155 // define (because we only get a single digit for the minor and micro
156 // revision numbers). So, we limit them to the maximum representable
157 // version.
158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159 char Str[7];
160 if (Maj < 10 || (Maj == 10 && Min < 10)) {
161 Str[0] = '0' + (Maj / 10);
162 Str[1] = '0' + (Maj % 10);
163 Str[2] = '0' + std::min(Min, 9U);
164 Str[3] = '0' + std::min(Rev, 9U);
165 Str[4] = '\0';
166 } else {
167 // Handle versions > 10.9.
168 Str[0] = '0' + (Maj / 10);
169 Str[1] = '0' + (Maj % 10);
170 Str[2] = '0' + (Min / 10);
171 Str[3] = '0' + (Min % 10);
172 Str[4] = '0' + (Rev / 10);
173 Str[5] = '0' + (Rev % 10);
174 Str[6] = '\0';
175 }
176 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
177 }
178
179 // Tell users about the kernel if there is one.
180 if (Triple.isOSDarwin())
181 Builder.defineMacro("__MACH__");
182
183 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
184 }
185
186 namespace {
187 // CloudABI Target
188 template <typename Target>
189 class CloudABITargetInfo : public OSTargetInfo<Target> {
190 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const191 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
192 MacroBuilder &Builder) const override {
193 Builder.defineMacro("__CloudABI__");
194 Builder.defineMacro("__ELF__");
195
196 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
197 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
198 Builder.defineMacro("__STDC_UTF_16__");
199 Builder.defineMacro("__STDC_UTF_32__");
200 }
201
202 public:
CloudABITargetInfo(const llvm::Triple & Triple)203 CloudABITargetInfo(const llvm::Triple &Triple)
204 : OSTargetInfo<Target>(Triple) {
205 this->UserLabelPrefix = "";
206 }
207 };
208
209 template<typename Target>
210 class DarwinTargetInfo : public OSTargetInfo<Target> {
211 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const212 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
213 MacroBuilder &Builder) const override {
214 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
215 this->PlatformMinVersion);
216 }
217
218 public:
DarwinTargetInfo(const llvm::Triple & Triple)219 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
220 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
221 this->MCountName = "\01mcount";
222 }
223
isValidSectionSpecifier(StringRef SR) const224 std::string isValidSectionSpecifier(StringRef SR) const override {
225 // Let MCSectionMachO validate this.
226 StringRef Segment, Section;
227 unsigned TAA, StubSize;
228 bool HasTAA;
229 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
230 TAA, HasTAA, StubSize);
231 }
232
getStaticInitSectionSpecifier() const233 const char *getStaticInitSectionSpecifier() const override {
234 // FIXME: We should return 0 when building kexts.
235 return "__TEXT,__StaticInit,regular,pure_instructions";
236 }
237
238 /// Darwin does not support protected visibility. Darwin's "default"
239 /// is very similar to ELF's "protected"; Darwin requires a "weak"
240 /// attribute on declarations that can be dynamically replaced.
hasProtectedVisibility() const241 bool hasProtectedVisibility() const override {
242 return false;
243 }
244 };
245
246
247 // DragonFlyBSD Target
248 template<typename Target>
249 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
250 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const251 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
252 MacroBuilder &Builder) const override {
253 // DragonFly defines; list based off of gcc output
254 Builder.defineMacro("__DragonFly__");
255 Builder.defineMacro("__DragonFly_cc_version", "100001");
256 Builder.defineMacro("__ELF__");
257 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
258 Builder.defineMacro("__tune_i386__");
259 DefineStd(Builder, "unix", Opts);
260 }
261 public:
DragonFlyBSDTargetInfo(const llvm::Triple & Triple)262 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
263 : OSTargetInfo<Target>(Triple) {
264 this->UserLabelPrefix = "";
265
266 switch (Triple.getArch()) {
267 default:
268 case llvm::Triple::x86:
269 case llvm::Triple::x86_64:
270 this->MCountName = ".mcount";
271 break;
272 }
273 }
274 };
275
276 // FreeBSD Target
277 template<typename Target>
278 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
279 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const280 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
281 MacroBuilder &Builder) const override {
282 // FreeBSD defines; list based off of gcc output
283
284 unsigned Release = Triple.getOSMajorVersion();
285 if (Release == 0U)
286 Release = 8;
287
288 Builder.defineMacro("__FreeBSD__", Twine(Release));
289 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
290 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
291 DefineStd(Builder, "unix", Opts);
292 Builder.defineMacro("__ELF__");
293
294 // On FreeBSD, wchar_t contains the number of the code point as
295 // used by the character set of the locale. These character sets are
296 // not necessarily a superset of ASCII.
297 //
298 // FIXME: This is wrong; the macro refers to the numerical values
299 // of wchar_t *literals*, which are not locale-dependent. However,
300 // FreeBSD systems apparently depend on us getting this wrong, and
301 // setting this to 1 is conforming even if all the basic source
302 // character literals have the same encoding as char and wchar_t.
303 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
304 }
305 public:
FreeBSDTargetInfo(const llvm::Triple & Triple)306 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
307 this->UserLabelPrefix = "";
308
309 switch (Triple.getArch()) {
310 default:
311 case llvm::Triple::x86:
312 case llvm::Triple::x86_64:
313 this->MCountName = ".mcount";
314 break;
315 case llvm::Triple::mips:
316 case llvm::Triple::mipsel:
317 case llvm::Triple::ppc:
318 case llvm::Triple::ppc64:
319 case llvm::Triple::ppc64le:
320 this->MCountName = "_mcount";
321 break;
322 case llvm::Triple::arm:
323 this->MCountName = "__mcount";
324 break;
325 }
326 }
327 };
328
329 // GNU/kFreeBSD Target
330 template<typename Target>
331 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
332 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
334 MacroBuilder &Builder) const override {
335 // GNU/kFreeBSD defines; list based off of gcc output
336
337 DefineStd(Builder, "unix", Opts);
338 Builder.defineMacro("__FreeBSD_kernel__");
339 Builder.defineMacro("__GLIBC__");
340 Builder.defineMacro("__ELF__");
341 if (Opts.POSIXThreads)
342 Builder.defineMacro("_REENTRANT");
343 if (Opts.CPlusPlus)
344 Builder.defineMacro("_GNU_SOURCE");
345 }
346 public:
KFreeBSDTargetInfo(const llvm::Triple & Triple)347 KFreeBSDTargetInfo(const llvm::Triple &Triple)
348 : OSTargetInfo<Target>(Triple) {
349 this->UserLabelPrefix = "";
350 }
351 };
352
353 // Minix Target
354 template<typename Target>
355 class MinixTargetInfo : public OSTargetInfo<Target> {
356 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const357 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
358 MacroBuilder &Builder) const override {
359 // Minix defines
360
361 Builder.defineMacro("__minix", "3");
362 Builder.defineMacro("_EM_WSIZE", "4");
363 Builder.defineMacro("_EM_PSIZE", "4");
364 Builder.defineMacro("_EM_SSIZE", "2");
365 Builder.defineMacro("_EM_LSIZE", "4");
366 Builder.defineMacro("_EM_FSIZE", "4");
367 Builder.defineMacro("_EM_DSIZE", "8");
368 Builder.defineMacro("__ELF__");
369 DefineStd(Builder, "unix", Opts);
370 }
371 public:
MinixTargetInfo(const llvm::Triple & Triple)372 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
373 this->UserLabelPrefix = "";
374 }
375 };
376
377 // Linux target
378 template<typename Target>
379 class LinuxTargetInfo : public OSTargetInfo<Target> {
380 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const381 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
382 MacroBuilder &Builder) const override {
383 // Linux defines; list based off of gcc output
384 DefineStd(Builder, "unix", Opts);
385 DefineStd(Builder, "linux", Opts);
386 Builder.defineMacro("__gnu_linux__");
387 Builder.defineMacro("__ELF__");
388 if (Triple.getEnvironment() == llvm::Triple::Android) {
389 Builder.defineMacro("__ANDROID__", "1");
390 unsigned Maj, Min, Rev;
391 Triple.getOSVersion(Maj, Min, Rev);
392 this->PlatformName = "android";
393 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
394 }
395 if (Opts.POSIXThreads)
396 Builder.defineMacro("_REENTRANT");
397 if (Opts.CPlusPlus)
398 Builder.defineMacro("_GNU_SOURCE");
399 }
400 public:
LinuxTargetInfo(const llvm::Triple & Triple)401 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
402 this->UserLabelPrefix = "";
403 this->WIntType = TargetInfo::UnsignedInt;
404
405 switch (Triple.getArch()) {
406 default:
407 break;
408 case llvm::Triple::ppc:
409 case llvm::Triple::ppc64:
410 case llvm::Triple::ppc64le:
411 this->MCountName = "_mcount";
412 break;
413 }
414 }
415
getStaticInitSectionSpecifier() const416 const char *getStaticInitSectionSpecifier() const override {
417 return ".text.startup";
418 }
419 };
420
421 // NetBSD Target
422 template<typename Target>
423 class NetBSDTargetInfo : public OSTargetInfo<Target> {
424 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
426 MacroBuilder &Builder) const override {
427 // NetBSD defines; list based off of gcc output
428 Builder.defineMacro("__NetBSD__");
429 Builder.defineMacro("__unix__");
430 Builder.defineMacro("__ELF__");
431 if (Opts.POSIXThreads)
432 Builder.defineMacro("_POSIX_THREADS");
433
434 switch (Triple.getArch()) {
435 default:
436 break;
437 case llvm::Triple::arm:
438 case llvm::Triple::armeb:
439 case llvm::Triple::thumb:
440 case llvm::Triple::thumbeb:
441 Builder.defineMacro("__ARM_DWARF_EH__");
442 break;
443 }
444 }
445 public:
NetBSDTargetInfo(const llvm::Triple & Triple)446 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
447 this->UserLabelPrefix = "";
448 this->MCountName = "_mcount";
449 }
450 };
451
452 // OpenBSD Target
453 template<typename Target>
454 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
455 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const456 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
457 MacroBuilder &Builder) const override {
458 // OpenBSD defines; list based off of gcc output
459
460 Builder.defineMacro("__OpenBSD__");
461 DefineStd(Builder, "unix", Opts);
462 Builder.defineMacro("__ELF__");
463 if (Opts.POSIXThreads)
464 Builder.defineMacro("_REENTRANT");
465 }
466 public:
OpenBSDTargetInfo(const llvm::Triple & Triple)467 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
468 this->UserLabelPrefix = "";
469 this->TLSSupported = false;
470
471 switch (Triple.getArch()) {
472 default:
473 case llvm::Triple::x86:
474 case llvm::Triple::x86_64:
475 case llvm::Triple::arm:
476 case llvm::Triple::sparc:
477 this->MCountName = "__mcount";
478 break;
479 case llvm::Triple::mips64:
480 case llvm::Triple::mips64el:
481 case llvm::Triple::ppc:
482 case llvm::Triple::sparcv9:
483 this->MCountName = "_mcount";
484 break;
485 }
486 }
487 };
488
489 // Bitrig Target
490 template<typename Target>
491 class BitrigTargetInfo : public OSTargetInfo<Target> {
492 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const493 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
494 MacroBuilder &Builder) const override {
495 // Bitrig defines; list based off of gcc output
496
497 Builder.defineMacro("__Bitrig__");
498 DefineStd(Builder, "unix", Opts);
499 Builder.defineMacro("__ELF__");
500 if (Opts.POSIXThreads)
501 Builder.defineMacro("_REENTRANT");
502
503 switch (Triple.getArch()) {
504 default:
505 break;
506 case llvm::Triple::arm:
507 case llvm::Triple::armeb:
508 case llvm::Triple::thumb:
509 case llvm::Triple::thumbeb:
510 Builder.defineMacro("__ARM_DWARF_EH__");
511 break;
512 }
513 }
514 public:
BitrigTargetInfo(const llvm::Triple & Triple)515 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
516 this->UserLabelPrefix = "";
517 this->MCountName = "__mcount";
518 }
519 };
520
521 // PSP Target
522 template<typename Target>
523 class PSPTargetInfo : public OSTargetInfo<Target> {
524 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const525 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
526 MacroBuilder &Builder) const override {
527 // PSP defines; list based on the output of the pspdev gcc toolchain.
528 Builder.defineMacro("PSP");
529 Builder.defineMacro("_PSP");
530 Builder.defineMacro("__psp__");
531 Builder.defineMacro("__ELF__");
532 }
533 public:
PSPTargetInfo(const llvm::Triple & Triple)534 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
535 this->UserLabelPrefix = "";
536 }
537 };
538
539 // PS3 PPU Target
540 template<typename Target>
541 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
542 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const543 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
544 MacroBuilder &Builder) const override {
545 // PS3 PPU defines.
546 Builder.defineMacro("__PPC__");
547 Builder.defineMacro("__PPU__");
548 Builder.defineMacro("__CELLOS_LV2__");
549 Builder.defineMacro("__ELF__");
550 Builder.defineMacro("__LP32__");
551 Builder.defineMacro("_ARCH_PPC64");
552 Builder.defineMacro("__powerpc64__");
553 }
554 public:
PS3PPUTargetInfo(const llvm::Triple & Triple)555 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
556 this->UserLabelPrefix = "";
557 this->LongWidth = this->LongAlign = 32;
558 this->PointerWidth = this->PointerAlign = 32;
559 this->IntMaxType = TargetInfo::SignedLongLong;
560 this->Int64Type = TargetInfo::SignedLongLong;
561 this->SizeType = TargetInfo::UnsignedInt;
562 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
563 }
564 };
565
566 template <typename Target>
567 class PS4OSTargetInfo : public OSTargetInfo<Target> {
568 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const569 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
570 MacroBuilder &Builder) const override {
571 Builder.defineMacro("__FreeBSD__", "9");
572 Builder.defineMacro("__FreeBSD_cc_version", "900001");
573 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
574 DefineStd(Builder, "unix", Opts);
575 Builder.defineMacro("__ELF__");
576 Builder.defineMacro("__PS4__");
577 }
578 public:
PS4OSTargetInfo(const llvm::Triple & Triple)579 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
580 this->WCharType = this->UnsignedShort;
581
582 this->UserLabelPrefix = "";
583
584 switch (Triple.getArch()) {
585 default:
586 case llvm::Triple::x86_64:
587 this->MCountName = ".mcount";
588 break;
589 }
590 }
591 };
592
593 // Solaris target
594 template<typename Target>
595 class SolarisTargetInfo : public OSTargetInfo<Target> {
596 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const597 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
598 MacroBuilder &Builder) const override {
599 DefineStd(Builder, "sun", Opts);
600 DefineStd(Builder, "unix", Opts);
601 Builder.defineMacro("__ELF__");
602 Builder.defineMacro("__svr4__");
603 Builder.defineMacro("__SVR4");
604 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
605 // newer, but to 500 for everything else. feature_test.h has a check to
606 // ensure that you are not using C99 with an old version of X/Open or C89
607 // with a new version.
608 if (Opts.C99)
609 Builder.defineMacro("_XOPEN_SOURCE", "600");
610 else
611 Builder.defineMacro("_XOPEN_SOURCE", "500");
612 if (Opts.CPlusPlus)
613 Builder.defineMacro("__C99FEATURES__");
614 Builder.defineMacro("_LARGEFILE_SOURCE");
615 Builder.defineMacro("_LARGEFILE64_SOURCE");
616 Builder.defineMacro("__EXTENSIONS__");
617 Builder.defineMacro("_REENTRANT");
618 }
619 public:
SolarisTargetInfo(const llvm::Triple & Triple)620 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
621 this->UserLabelPrefix = "";
622 this->WCharType = this->SignedInt;
623 // FIXME: WIntType should be SignedLong
624 }
625 };
626
627 // Windows target
628 template<typename Target>
629 class WindowsTargetInfo : public OSTargetInfo<Target> {
630 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const631 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
632 MacroBuilder &Builder) const override {
633 Builder.defineMacro("_WIN32");
634 }
getVisualStudioDefines(const LangOptions & Opts,MacroBuilder & Builder) const635 void getVisualStudioDefines(const LangOptions &Opts,
636 MacroBuilder &Builder) const {
637 if (Opts.CPlusPlus) {
638 if (Opts.RTTIData)
639 Builder.defineMacro("_CPPRTTI");
640
641 if (Opts.CXXExceptions)
642 Builder.defineMacro("_CPPUNWIND");
643 }
644
645 if (!Opts.CharIsSigned)
646 Builder.defineMacro("_CHAR_UNSIGNED");
647
648 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
649 // but it works for now.
650 if (Opts.POSIXThreads)
651 Builder.defineMacro("_MT");
652
653 if (Opts.MSCompatibilityVersion) {
654 Builder.defineMacro("_MSC_VER",
655 Twine(Opts.MSCompatibilityVersion / 100000));
656 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
657 // FIXME We cannot encode the revision information into 32-bits
658 Builder.defineMacro("_MSC_BUILD", Twine(1));
659
660 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(19))
661 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
662 }
663
664 if (Opts.MicrosoftExt) {
665 Builder.defineMacro("_MSC_EXTENSIONS");
666
667 if (Opts.CPlusPlus11) {
668 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
669 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
670 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
671 }
672 }
673
674 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
675 }
676
677 public:
WindowsTargetInfo(const llvm::Triple & Triple)678 WindowsTargetInfo(const llvm::Triple &Triple)
679 : OSTargetInfo<Target>(Triple) {}
680 };
681
682 template <typename Target>
683 class NaClTargetInfo : public OSTargetInfo<Target> {
684 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const685 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
686 MacroBuilder &Builder) const override {
687 if (Opts.POSIXThreads)
688 Builder.defineMacro("_REENTRANT");
689 if (Opts.CPlusPlus)
690 Builder.defineMacro("_GNU_SOURCE");
691
692 DefineStd(Builder, "unix", Opts);
693 Builder.defineMacro("__ELF__");
694 Builder.defineMacro("__native_client__");
695 }
696
697 public:
NaClTargetInfo(const llvm::Triple & Triple)698 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
699 this->UserLabelPrefix = "";
700 this->LongAlign = 32;
701 this->LongWidth = 32;
702 this->PointerAlign = 32;
703 this->PointerWidth = 32;
704 this->IntMaxType = TargetInfo::SignedLongLong;
705 this->Int64Type = TargetInfo::SignedLongLong;
706 this->DoubleAlign = 64;
707 this->LongDoubleWidth = 64;
708 this->LongDoubleAlign = 64;
709 this->LongLongWidth = 64;
710 this->LongLongAlign = 64;
711 this->SizeType = TargetInfo::UnsignedInt;
712 this->PtrDiffType = TargetInfo::SignedInt;
713 this->IntPtrType = TargetInfo::SignedInt;
714 // RegParmMax is inherited from the underlying architecture
715 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
716 if (Triple.getArch() == llvm::Triple::arm) {
717 // Handled in ARM's setABI().
718 } else if (Triple.getArch() == llvm::Triple::x86) {
719 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
720 } else if (Triple.getArch() == llvm::Triple::x86_64) {
721 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
722 } else if (Triple.getArch() == llvm::Triple::mipsel) {
723 // Handled on mips' setDescriptionString.
724 } else {
725 assert(Triple.getArch() == llvm::Triple::le32);
726 this->DescriptionString = "e-p:32:32-i64:64";
727 }
728 }
729 };
730
731 //===----------------------------------------------------------------------===//
732 // Specific target implementations.
733 //===----------------------------------------------------------------------===//
734
735 // PPC abstract base class
736 class PPCTargetInfo : public TargetInfo {
737 static const Builtin::Info BuiltinInfo[];
738 static const char * const GCCRegNames[];
739 static const TargetInfo::GCCRegAlias GCCRegAliases[];
740 std::string CPU;
741
742 // Target cpu features.
743 bool HasVSX;
744 bool HasP8Vector;
745 bool HasP8Crypto;
746 bool HasDirectMove;
747 bool HasQPX;
748 bool HasHTM;
749 bool HasBPERMD;
750 bool HasExtDiv;
751
752 protected:
753 std::string ABI;
754
755 public:
PPCTargetInfo(const llvm::Triple & Triple)756 PPCTargetInfo(const llvm::Triple &Triple)
757 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
758 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
759 HasBPERMD(false), HasExtDiv(false) {
760 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
761 LongDoubleWidth = LongDoubleAlign = 128;
762 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
763 }
764
765 /// \brief Flags for architecture specific defines.
766 typedef enum {
767 ArchDefineNone = 0,
768 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
769 ArchDefinePpcgr = 1 << 1,
770 ArchDefinePpcsq = 1 << 2,
771 ArchDefine440 = 1 << 3,
772 ArchDefine603 = 1 << 4,
773 ArchDefine604 = 1 << 5,
774 ArchDefinePwr4 = 1 << 6,
775 ArchDefinePwr5 = 1 << 7,
776 ArchDefinePwr5x = 1 << 8,
777 ArchDefinePwr6 = 1 << 9,
778 ArchDefinePwr6x = 1 << 10,
779 ArchDefinePwr7 = 1 << 11,
780 ArchDefinePwr8 = 1 << 12,
781 ArchDefineA2 = 1 << 13,
782 ArchDefineA2q = 1 << 14
783 } ArchDefineTypes;
784
785 // Note: GCC recognizes the following additional cpus:
786 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
787 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
788 // titan, rs64.
setCPU(const std::string & Name)789 bool setCPU(const std::string &Name) override {
790 bool CPUKnown = llvm::StringSwitch<bool>(Name)
791 .Case("generic", true)
792 .Case("440", true)
793 .Case("450", true)
794 .Case("601", true)
795 .Case("602", true)
796 .Case("603", true)
797 .Case("603e", true)
798 .Case("603ev", true)
799 .Case("604", true)
800 .Case("604e", true)
801 .Case("620", true)
802 .Case("630", true)
803 .Case("g3", true)
804 .Case("7400", true)
805 .Case("g4", true)
806 .Case("7450", true)
807 .Case("g4+", true)
808 .Case("750", true)
809 .Case("970", true)
810 .Case("g5", true)
811 .Case("a2", true)
812 .Case("a2q", true)
813 .Case("e500mc", true)
814 .Case("e5500", true)
815 .Case("power3", true)
816 .Case("pwr3", true)
817 .Case("power4", true)
818 .Case("pwr4", true)
819 .Case("power5", true)
820 .Case("pwr5", true)
821 .Case("power5x", true)
822 .Case("pwr5x", true)
823 .Case("power6", true)
824 .Case("pwr6", true)
825 .Case("power6x", true)
826 .Case("pwr6x", true)
827 .Case("power7", true)
828 .Case("pwr7", true)
829 .Case("power8", true)
830 .Case("pwr8", true)
831 .Case("powerpc", true)
832 .Case("ppc", true)
833 .Case("powerpc64", true)
834 .Case("ppc64", true)
835 .Case("powerpc64le", true)
836 .Case("ppc64le", true)
837 .Default(false);
838
839 if (CPUKnown)
840 CPU = Name;
841
842 return CPUKnown;
843 }
844
845
getABI() const846 StringRef getABI() const override { return ABI; }
847
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const848 void getTargetBuiltins(const Builtin::Info *&Records,
849 unsigned &NumRecords) const override {
850 Records = BuiltinInfo;
851 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
852 }
853
isCLZForZeroUndef() const854 bool isCLZForZeroUndef() const override { return false; }
855
856 void getTargetDefines(const LangOptions &Opts,
857 MacroBuilder &Builder) const override;
858
859 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
860
861 bool handleTargetFeatures(std::vector<std::string> &Features,
862 DiagnosticsEngine &Diags) override;
863 bool hasFeature(StringRef Feature) const override;
864
865 void getGCCRegNames(const char * const *&Names,
866 unsigned &NumNames) const override;
867 void getGCCRegAliases(const GCCRegAlias *&Aliases,
868 unsigned &NumAliases) const override;
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const869 bool validateAsmConstraint(const char *&Name,
870 TargetInfo::ConstraintInfo &Info) const override {
871 switch (*Name) {
872 default: return false;
873 case 'O': // Zero
874 break;
875 case 'b': // Base register
876 case 'f': // Floating point register
877 Info.setAllowsRegister();
878 break;
879 // FIXME: The following are added to allow parsing.
880 // I just took a guess at what the actions should be.
881 // Also, is more specific checking needed? I.e. specific registers?
882 case 'd': // Floating point register (containing 64-bit value)
883 case 'v': // Altivec vector register
884 Info.setAllowsRegister();
885 break;
886 case 'w':
887 switch (Name[1]) {
888 case 'd':// VSX vector register to hold vector double data
889 case 'f':// VSX vector register to hold vector float data
890 case 's':// VSX vector register to hold scalar float data
891 case 'a':// Any VSX register
892 case 'c':// An individual CR bit
893 break;
894 default:
895 return false;
896 }
897 Info.setAllowsRegister();
898 Name++; // Skip over 'w'.
899 break;
900 case 'h': // `MQ', `CTR', or `LINK' register
901 case 'q': // `MQ' register
902 case 'c': // `CTR' register
903 case 'l': // `LINK' register
904 case 'x': // `CR' register (condition register) number 0
905 case 'y': // `CR' register (condition register)
906 case 'z': // `XER[CA]' carry bit (part of the XER register)
907 Info.setAllowsRegister();
908 break;
909 case 'I': // Signed 16-bit constant
910 case 'J': // Unsigned 16-bit constant shifted left 16 bits
911 // (use `L' instead for SImode constants)
912 case 'K': // Unsigned 16-bit constant
913 case 'L': // Signed 16-bit constant shifted left 16 bits
914 case 'M': // Constant larger than 31
915 case 'N': // Exact power of 2
916 case 'P': // Constant whose negation is a signed 16-bit constant
917 case 'G': // Floating point constant that can be loaded into a
918 // register with one instruction per word
919 case 'H': // Integer/Floating point constant that can be loaded
920 // into a register using three instructions
921 break;
922 case 'm': // Memory operand. Note that on PowerPC targets, m can
923 // include addresses that update the base register. It
924 // is therefore only safe to use `m' in an asm statement
925 // if that asm statement accesses the operand exactly once.
926 // The asm statement must also use `%U<opno>' as a
927 // placeholder for the "update" flag in the corresponding
928 // load or store instruction. For example:
929 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
930 // is correct but:
931 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
932 // is not. Use es rather than m if you don't want the base
933 // register to be updated.
934 case 'e':
935 if (Name[1] != 's')
936 return false;
937 // es: A "stable" memory operand; that is, one which does not
938 // include any automodification of the base register. Unlike
939 // `m', this constraint can be used in asm statements that
940 // might access the operand several times, or that might not
941 // access it at all.
942 Info.setAllowsMemory();
943 Name++; // Skip over 'e'.
944 break;
945 case 'Q': // Memory operand that is an offset from a register (it is
946 // usually better to use `m' or `es' in asm statements)
947 case 'Z': // Memory operand that is an indexed or indirect from a
948 // register (it is usually better to use `m' or `es' in
949 // asm statements)
950 Info.setAllowsMemory();
951 Info.setAllowsRegister();
952 break;
953 case 'R': // AIX TOC entry
954 case 'a': // Address operand that is an indexed or indirect from a
955 // register (`p' is preferable for asm statements)
956 case 'S': // Constant suitable as a 64-bit mask operand
957 case 'T': // Constant suitable as a 32-bit mask operand
958 case 'U': // System V Release 4 small data area reference
959 case 't': // AND masks that can be performed by two rldic{l, r}
960 // instructions
961 case 'W': // Vector constant that does not require memory
962 case 'j': // Vector constant that is all zeros.
963 break;
964 // End FIXME.
965 }
966 return true;
967 }
convertConstraint(const char * & Constraint) const968 std::string convertConstraint(const char *&Constraint) const override {
969 std::string R;
970 switch (*Constraint) {
971 case 'e':
972 case 'w':
973 // Two-character constraint; add "^" hint for later parsing.
974 R = std::string("^") + std::string(Constraint, 2);
975 Constraint++;
976 break;
977 default:
978 return TargetInfo::convertConstraint(Constraint);
979 }
980 return R;
981 }
getClobbers() const982 const char *getClobbers() const override {
983 return "";
984 }
getEHDataRegisterNumber(unsigned RegNo) const985 int getEHDataRegisterNumber(unsigned RegNo) const override {
986 if (RegNo == 0) return 3;
987 if (RegNo == 1) return 4;
988 return -1;
989 }
990
hasSjLjLowering() const991 bool hasSjLjLowering() const override {
992 return true;
993 }
994 };
995
996 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
997 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
998 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
999 ALL_LANGUAGES },
1000 #include "clang/Basic/BuiltinsPPC.def"
1001 };
1002
1003 /// handleTargetFeatures - Perform initialization based on the user
1004 /// configured set of features.
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)1005 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1006 DiagnosticsEngine &Diags) {
1007 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
1008 // Ignore disabled features.
1009 if (Features[i][0] == '-')
1010 continue;
1011
1012 StringRef Feature = StringRef(Features[i]).substr(1);
1013
1014 if (Feature == "vsx") {
1015 HasVSX = true;
1016 continue;
1017 }
1018
1019 if (Feature == "bpermd") {
1020 HasBPERMD = true;
1021 continue;
1022 }
1023
1024 if (Feature == "extdiv") {
1025 HasExtDiv = true;
1026 continue;
1027 }
1028
1029 if (Feature == "power8-vector") {
1030 HasP8Vector = true;
1031 continue;
1032 }
1033
1034 if (Feature == "crypto") {
1035 HasP8Crypto = true;
1036 continue;
1037 }
1038
1039 if (Feature == "direct-move") {
1040 HasDirectMove = true;
1041 continue;
1042 }
1043
1044 if (Feature == "qpx") {
1045 HasQPX = true;
1046 continue;
1047 }
1048
1049 if (Feature == "htm") {
1050 HasHTM = true;
1051 continue;
1052 }
1053
1054 // TODO: Finish this list and add an assert that we've handled them
1055 // all.
1056 }
1057
1058 return true;
1059 }
1060
1061 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1062 /// #defines that are not tied to a specific subtarget.
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const1063 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1064 MacroBuilder &Builder) const {
1065 // Target identification.
1066 Builder.defineMacro("__ppc__");
1067 Builder.defineMacro("__PPC__");
1068 Builder.defineMacro("_ARCH_PPC");
1069 Builder.defineMacro("__powerpc__");
1070 Builder.defineMacro("__POWERPC__");
1071 if (PointerWidth == 64) {
1072 Builder.defineMacro("_ARCH_PPC64");
1073 Builder.defineMacro("__powerpc64__");
1074 Builder.defineMacro("__ppc64__");
1075 Builder.defineMacro("__PPC64__");
1076 }
1077
1078 // Target properties.
1079 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1080 Builder.defineMacro("_LITTLE_ENDIAN");
1081 } else {
1082 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1083 getTriple().getOS() != llvm::Triple::OpenBSD)
1084 Builder.defineMacro("_BIG_ENDIAN");
1085 }
1086
1087 // ABI options.
1088 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1089 Builder.defineMacro("_CALL_ELF", "1");
1090 if (ABI == "elfv2")
1091 Builder.defineMacro("_CALL_ELF", "2");
1092
1093 // Subtarget options.
1094 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1095 Builder.defineMacro("__REGISTER_PREFIX__", "");
1096
1097 // FIXME: Should be controlled by command line option.
1098 if (LongDoubleWidth == 128)
1099 Builder.defineMacro("__LONG_DOUBLE_128__");
1100
1101 if (Opts.AltiVec) {
1102 Builder.defineMacro("__VEC__", "10206");
1103 Builder.defineMacro("__ALTIVEC__");
1104 }
1105
1106 // CPU identification.
1107 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1108 .Case("440", ArchDefineName)
1109 .Case("450", ArchDefineName | ArchDefine440)
1110 .Case("601", ArchDefineName)
1111 .Case("602", ArchDefineName | ArchDefinePpcgr)
1112 .Case("603", ArchDefineName | ArchDefinePpcgr)
1113 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1114 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1115 .Case("604", ArchDefineName | ArchDefinePpcgr)
1116 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1117 .Case("620", ArchDefineName | ArchDefinePpcgr)
1118 .Case("630", ArchDefineName | ArchDefinePpcgr)
1119 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1120 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1121 .Case("750", ArchDefineName | ArchDefinePpcgr)
1122 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1123 | ArchDefinePpcsq)
1124 .Case("a2", ArchDefineA2)
1125 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1126 .Case("pwr3", ArchDefinePpcgr)
1127 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1128 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1129 | ArchDefinePpcsq)
1130 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1131 | ArchDefinePpcgr | ArchDefinePpcsq)
1132 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1133 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1134 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1135 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1136 | ArchDefinePpcsq)
1137 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1138 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1139 | ArchDefinePpcgr | ArchDefinePpcsq)
1140 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1141 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1142 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1143 .Case("power3", ArchDefinePpcgr)
1144 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1145 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1146 | ArchDefinePpcsq)
1147 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1148 | ArchDefinePpcgr | ArchDefinePpcsq)
1149 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1150 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1151 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1152 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1153 | ArchDefinePpcsq)
1154 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1155 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1156 | ArchDefinePpcgr | ArchDefinePpcsq)
1157 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1158 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1159 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1160 .Default(ArchDefineNone);
1161
1162 if (defs & ArchDefineName)
1163 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1164 if (defs & ArchDefinePpcgr)
1165 Builder.defineMacro("_ARCH_PPCGR");
1166 if (defs & ArchDefinePpcsq)
1167 Builder.defineMacro("_ARCH_PPCSQ");
1168 if (defs & ArchDefine440)
1169 Builder.defineMacro("_ARCH_440");
1170 if (defs & ArchDefine603)
1171 Builder.defineMacro("_ARCH_603");
1172 if (defs & ArchDefine604)
1173 Builder.defineMacro("_ARCH_604");
1174 if (defs & ArchDefinePwr4)
1175 Builder.defineMacro("_ARCH_PWR4");
1176 if (defs & ArchDefinePwr5)
1177 Builder.defineMacro("_ARCH_PWR5");
1178 if (defs & ArchDefinePwr5x)
1179 Builder.defineMacro("_ARCH_PWR5X");
1180 if (defs & ArchDefinePwr6)
1181 Builder.defineMacro("_ARCH_PWR6");
1182 if (defs & ArchDefinePwr6x)
1183 Builder.defineMacro("_ARCH_PWR6X");
1184 if (defs & ArchDefinePwr7)
1185 Builder.defineMacro("_ARCH_PWR7");
1186 if (defs & ArchDefinePwr8)
1187 Builder.defineMacro("_ARCH_PWR8");
1188 if (defs & ArchDefineA2)
1189 Builder.defineMacro("_ARCH_A2");
1190 if (defs & ArchDefineA2q) {
1191 Builder.defineMacro("_ARCH_A2Q");
1192 Builder.defineMacro("_ARCH_QP");
1193 }
1194
1195 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1196 Builder.defineMacro("__bg__");
1197 Builder.defineMacro("__THW_BLUEGENE__");
1198 Builder.defineMacro("__bgq__");
1199 Builder.defineMacro("__TOS_BGQ__");
1200 }
1201
1202 if (HasVSX)
1203 Builder.defineMacro("__VSX__");
1204 if (HasP8Vector)
1205 Builder.defineMacro("__POWER8_VECTOR__");
1206 if (HasP8Crypto)
1207 Builder.defineMacro("__CRYPTO__");
1208 if (HasHTM)
1209 Builder.defineMacro("__HTM__");
1210
1211 // FIXME: The following are not yet generated here by Clang, but are
1212 // generated by GCC:
1213 //
1214 // _SOFT_FLOAT_
1215 // __RECIP_PRECISION__
1216 // __APPLE_ALTIVEC__
1217 // __RECIP__
1218 // __RECIPF__
1219 // __RSQRTE__
1220 // __RSQRTEF__
1221 // _SOFT_DOUBLE_
1222 // __NO_LWSYNC__
1223 // __HAVE_BSWAP__
1224 // __LONGDOUBLE128
1225 // __CMODEL_MEDIUM__
1226 // __CMODEL_LARGE__
1227 // _CALL_SYSV
1228 // _CALL_DARWIN
1229 // __NO_FPRS__
1230 }
1231
getDefaultFeatures(llvm::StringMap<bool> & Features) const1232 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1233 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1234 .Case("7400", true)
1235 .Case("g4", true)
1236 .Case("7450", true)
1237 .Case("g4+", true)
1238 .Case("970", true)
1239 .Case("g5", true)
1240 .Case("pwr6", true)
1241 .Case("pwr7", true)
1242 .Case("pwr8", true)
1243 .Case("ppc64", true)
1244 .Case("ppc64le", true)
1245 .Default(false);
1246
1247 Features["qpx"] = (CPU == "a2q");
1248 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1249 .Case("ppc64le", true)
1250 .Case("pwr8", true)
1251 .Default(false);
1252 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1253 .Case("ppc64le", true)
1254 .Case("pwr8", true)
1255 .Default(false);
1256 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1257 .Case("ppc64le", true)
1258 .Case("pwr8", true)
1259 .Case("pwr7", true)
1260 .Default(false);
1261 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1262 .Case("ppc64le", true)
1263 .Case("pwr8", true)
1264 .Case("pwr7", true)
1265 .Default(false);
1266 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1267 .Case("ppc64le", true)
1268 .Case("pwr8", true)
1269 .Default(false);
1270 }
1271
hasFeature(StringRef Feature) const1272 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1273 return llvm::StringSwitch<bool>(Feature)
1274 .Case("powerpc", true)
1275 .Case("vsx", HasVSX)
1276 .Case("power8-vector", HasP8Vector)
1277 .Case("crypto", HasP8Crypto)
1278 .Case("direct-move", HasDirectMove)
1279 .Case("qpx", HasQPX)
1280 .Case("htm", HasHTM)
1281 .Case("bpermd", HasBPERMD)
1282 .Case("extdiv", HasExtDiv)
1283 .Default(false);
1284 }
1285
1286 const char * const PPCTargetInfo::GCCRegNames[] = {
1287 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1288 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1289 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1290 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1291 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1292 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1293 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1294 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1295 "mq", "lr", "ctr", "ap",
1296 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1297 "xer",
1298 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1299 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1300 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1301 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1302 "vrsave", "vscr",
1303 "spe_acc", "spefscr",
1304 "sfp"
1305 };
1306
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const1307 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1308 unsigned &NumNames) const {
1309 Names = GCCRegNames;
1310 NumNames = llvm::array_lengthof(GCCRegNames);
1311 }
1312
1313 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1314 // While some of these aliases do map to different registers
1315 // they still share the same register name.
1316 { { "0" }, "r0" },
1317 { { "1"}, "r1" },
1318 { { "2" }, "r2" },
1319 { { "3" }, "r3" },
1320 { { "4" }, "r4" },
1321 { { "5" }, "r5" },
1322 { { "6" }, "r6" },
1323 { { "7" }, "r7" },
1324 { { "8" }, "r8" },
1325 { { "9" }, "r9" },
1326 { { "10" }, "r10" },
1327 { { "11" }, "r11" },
1328 { { "12" }, "r12" },
1329 { { "13" }, "r13" },
1330 { { "14" }, "r14" },
1331 { { "15" }, "r15" },
1332 { { "16" }, "r16" },
1333 { { "17" }, "r17" },
1334 { { "18" }, "r18" },
1335 { { "19" }, "r19" },
1336 { { "20" }, "r20" },
1337 { { "21" }, "r21" },
1338 { { "22" }, "r22" },
1339 { { "23" }, "r23" },
1340 { { "24" }, "r24" },
1341 { { "25" }, "r25" },
1342 { { "26" }, "r26" },
1343 { { "27" }, "r27" },
1344 { { "28" }, "r28" },
1345 { { "29" }, "r29" },
1346 { { "30" }, "r30" },
1347 { { "31" }, "r31" },
1348 { { "fr0" }, "f0" },
1349 { { "fr1" }, "f1" },
1350 { { "fr2" }, "f2" },
1351 { { "fr3" }, "f3" },
1352 { { "fr4" }, "f4" },
1353 { { "fr5" }, "f5" },
1354 { { "fr6" }, "f6" },
1355 { { "fr7" }, "f7" },
1356 { { "fr8" }, "f8" },
1357 { { "fr9" }, "f9" },
1358 { { "fr10" }, "f10" },
1359 { { "fr11" }, "f11" },
1360 { { "fr12" }, "f12" },
1361 { { "fr13" }, "f13" },
1362 { { "fr14" }, "f14" },
1363 { { "fr15" }, "f15" },
1364 { { "fr16" }, "f16" },
1365 { { "fr17" }, "f17" },
1366 { { "fr18" }, "f18" },
1367 { { "fr19" }, "f19" },
1368 { { "fr20" }, "f20" },
1369 { { "fr21" }, "f21" },
1370 { { "fr22" }, "f22" },
1371 { { "fr23" }, "f23" },
1372 { { "fr24" }, "f24" },
1373 { { "fr25" }, "f25" },
1374 { { "fr26" }, "f26" },
1375 { { "fr27" }, "f27" },
1376 { { "fr28" }, "f28" },
1377 { { "fr29" }, "f29" },
1378 { { "fr30" }, "f30" },
1379 { { "fr31" }, "f31" },
1380 { { "cc" }, "cr0" },
1381 };
1382
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const1383 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1384 unsigned &NumAliases) const {
1385 Aliases = GCCRegAliases;
1386 NumAliases = llvm::array_lengthof(GCCRegAliases);
1387 }
1388
1389 class PPC32TargetInfo : public PPCTargetInfo {
1390 public:
PPC32TargetInfo(const llvm::Triple & Triple)1391 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1392 DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1393
1394 switch (getTriple().getOS()) {
1395 case llvm::Triple::Linux:
1396 case llvm::Triple::FreeBSD:
1397 case llvm::Triple::NetBSD:
1398 SizeType = UnsignedInt;
1399 PtrDiffType = SignedInt;
1400 IntPtrType = SignedInt;
1401 break;
1402 default:
1403 break;
1404 }
1405
1406 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1407 LongDoubleWidth = LongDoubleAlign = 64;
1408 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1409 }
1410
1411 // PPC32 supports atomics up to 4 bytes.
1412 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1413 }
1414
getBuiltinVaListKind() const1415 BuiltinVaListKind getBuiltinVaListKind() const override {
1416 // This is the ELF definition, and is overridden by the Darwin sub-target
1417 return TargetInfo::PowerABIBuiltinVaList;
1418 }
1419 };
1420
1421 // Note: ABI differences may eventually require us to have a separate
1422 // TargetInfo for little endian.
1423 class PPC64TargetInfo : public PPCTargetInfo {
1424 public:
PPC64TargetInfo(const llvm::Triple & Triple)1425 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1426 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1427 IntMaxType = SignedLong;
1428 Int64Type = SignedLong;
1429
1430 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1431 DescriptionString = "e-m:e-i64:64-n32:64";
1432 ABI = "elfv2";
1433 } else {
1434 DescriptionString = "E-m:e-i64:64-n32:64";
1435 ABI = "elfv1";
1436 }
1437
1438 switch (getTriple().getOS()) {
1439 case llvm::Triple::FreeBSD:
1440 LongDoubleWidth = LongDoubleAlign = 64;
1441 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1442 break;
1443 case llvm::Triple::NetBSD:
1444 IntMaxType = SignedLongLong;
1445 Int64Type = SignedLongLong;
1446 break;
1447 default:
1448 break;
1449 }
1450
1451 // PPC64 supports atomics up to 8 bytes.
1452 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1453 }
getBuiltinVaListKind() const1454 BuiltinVaListKind getBuiltinVaListKind() const override {
1455 return TargetInfo::CharPtrBuiltinVaList;
1456 }
1457 // PPC64 Linux-specifc ABI options.
setABI(const std::string & Name)1458 bool setABI(const std::string &Name) override {
1459 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1460 ABI = Name;
1461 return true;
1462 }
1463 return false;
1464 }
1465 };
1466
1467 class DarwinPPC32TargetInfo :
1468 public DarwinTargetInfo<PPC32TargetInfo> {
1469 public:
DarwinPPC32TargetInfo(const llvm::Triple & Triple)1470 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1471 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1472 HasAlignMac68kSupport = true;
1473 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1474 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1475 LongLongAlign = 32;
1476 SuitableAlign = 128;
1477 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1478 }
getBuiltinVaListKind() const1479 BuiltinVaListKind getBuiltinVaListKind() const override {
1480 return TargetInfo::CharPtrBuiltinVaList;
1481 }
1482 };
1483
1484 class DarwinPPC64TargetInfo :
1485 public DarwinTargetInfo<PPC64TargetInfo> {
1486 public:
DarwinPPC64TargetInfo(const llvm::Triple & Triple)1487 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1488 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1489 HasAlignMac68kSupport = true;
1490 SuitableAlign = 128;
1491 DescriptionString = "E-m:o-i64:64-n32:64";
1492 }
1493 };
1494
1495 static const unsigned NVPTXAddrSpaceMap[] = {
1496 1, // opencl_global
1497 3, // opencl_local
1498 4, // opencl_constant
1499 // FIXME: generic has to be added to the target
1500 0, // opencl_generic
1501 1, // cuda_device
1502 4, // cuda_constant
1503 3, // cuda_shared
1504 };
1505 class NVPTXTargetInfo : public TargetInfo {
1506 static const char * const GCCRegNames[];
1507 static const Builtin::Info BuiltinInfo[];
1508
1509 // The GPU profiles supported by the NVPTX backend
1510 enum GPUKind {
1511 GK_NONE,
1512 GK_SM20,
1513 GK_SM21,
1514 GK_SM30,
1515 GK_SM35,
1516 GK_SM37,
1517 } GPU;
1518
1519 public:
NVPTXTargetInfo(const llvm::Triple & Triple)1520 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1521 BigEndian = false;
1522 TLSSupported = false;
1523 LongWidth = LongAlign = 64;
1524 AddrSpaceMap = &NVPTXAddrSpaceMap;
1525 UseAddrSpaceMapMangling = true;
1526 // Define available target features
1527 // These must be defined in sorted order!
1528 NoAsmVariants = true;
1529 // Set the default GPU to sm20
1530 GPU = GK_SM20;
1531 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const1532 void getTargetDefines(const LangOptions &Opts,
1533 MacroBuilder &Builder) const override {
1534 Builder.defineMacro("__PTX__");
1535 Builder.defineMacro("__NVPTX__");
1536 if (Opts.CUDAIsDevice) {
1537 // Set __CUDA_ARCH__ for the GPU specified.
1538 std::string CUDAArchCode;
1539 switch (GPU) {
1540 case GK_SM20:
1541 CUDAArchCode = "200";
1542 break;
1543 case GK_SM21:
1544 CUDAArchCode = "210";
1545 break;
1546 case GK_SM30:
1547 CUDAArchCode = "300";
1548 break;
1549 case GK_SM35:
1550 CUDAArchCode = "350";
1551 break;
1552 case GK_SM37:
1553 CUDAArchCode = "370";
1554 break;
1555 default:
1556 llvm_unreachable("Unhandled target CPU");
1557 }
1558 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1559 }
1560 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const1561 void getTargetBuiltins(const Builtin::Info *&Records,
1562 unsigned &NumRecords) const override {
1563 Records = BuiltinInfo;
1564 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1565 }
hasFeature(StringRef Feature) const1566 bool hasFeature(StringRef Feature) const override {
1567 return Feature == "ptx" || Feature == "nvptx";
1568 }
1569
1570 void getGCCRegNames(const char * const *&Names,
1571 unsigned &NumNames) const override;
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const1572 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1573 unsigned &NumAliases) const override {
1574 // No aliases.
1575 Aliases = nullptr;
1576 NumAliases = 0;
1577 }
1578 bool
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const1579 validateAsmConstraint(const char *&Name,
1580 TargetInfo::ConstraintInfo &Info) const override {
1581 switch (*Name) {
1582 default: return false;
1583 case 'c':
1584 case 'h':
1585 case 'r':
1586 case 'l':
1587 case 'f':
1588 case 'd':
1589 Info.setAllowsRegister();
1590 return true;
1591 }
1592 }
getClobbers() const1593 const char *getClobbers() const override {
1594 // FIXME: Is this really right?
1595 return "";
1596 }
getBuiltinVaListKind() const1597 BuiltinVaListKind getBuiltinVaListKind() const override {
1598 // FIXME: implement
1599 return TargetInfo::CharPtrBuiltinVaList;
1600 }
setCPU(const std::string & Name)1601 bool setCPU(const std::string &Name) override {
1602 GPU = llvm::StringSwitch<GPUKind>(Name)
1603 .Case("sm_20", GK_SM20)
1604 .Case("sm_21", GK_SM21)
1605 .Case("sm_30", GK_SM30)
1606 .Case("sm_35", GK_SM35)
1607 .Case("sm_37", GK_SM37)
1608 .Default(GK_NONE);
1609
1610 return GPU != GK_NONE;
1611 }
1612 };
1613
1614 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1615 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1616 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1617 ALL_LANGUAGES },
1618 #include "clang/Basic/BuiltinsNVPTX.def"
1619 };
1620
1621 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1622 "r0"
1623 };
1624
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const1625 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1626 unsigned &NumNames) const {
1627 Names = GCCRegNames;
1628 NumNames = llvm::array_lengthof(GCCRegNames);
1629 }
1630
1631 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1632 public:
NVPTX32TargetInfo(const llvm::Triple & Triple)1633 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1634 PointerWidth = PointerAlign = 32;
1635 SizeType = TargetInfo::UnsignedInt;
1636 PtrDiffType = TargetInfo::SignedInt;
1637 IntPtrType = TargetInfo::SignedInt;
1638 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1639 }
1640 };
1641
1642 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1643 public:
NVPTX64TargetInfo(const llvm::Triple & Triple)1644 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1645 PointerWidth = PointerAlign = 64;
1646 SizeType = TargetInfo::UnsignedLong;
1647 PtrDiffType = TargetInfo::SignedLong;
1648 IntPtrType = TargetInfo::SignedLong;
1649 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1650 }
1651 };
1652
1653 static const unsigned R600AddrSpaceMap[] = {
1654 1, // opencl_global
1655 3, // opencl_local
1656 2, // opencl_constant
1657 4, // opencl_generic
1658 1, // cuda_device
1659 2, // cuda_constant
1660 3 // cuda_shared
1661 };
1662
1663 // If you edit the description strings, make sure you update
1664 // getPointerWidthV().
1665
1666 static const char *DescriptionStringR600 =
1667 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1668 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1669
1670 static const char *DescriptionStringR600DoubleOps =
1671 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1672 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1673
1674 static const char *DescriptionStringSI =
1675 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1676 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1677 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1678
1679 class R600TargetInfo : public TargetInfo {
1680 static const Builtin::Info BuiltinInfo[];
1681 static const char * const GCCRegNames[];
1682
1683 /// \brief The GPU profiles supported by the R600 target.
1684 enum GPUKind {
1685 GK_NONE,
1686 GK_R600,
1687 GK_R600_DOUBLE_OPS,
1688 GK_R700,
1689 GK_R700_DOUBLE_OPS,
1690 GK_EVERGREEN,
1691 GK_EVERGREEN_DOUBLE_OPS,
1692 GK_NORTHERN_ISLANDS,
1693 GK_CAYMAN,
1694 GK_SOUTHERN_ISLANDS,
1695 GK_SEA_ISLANDS
1696 } GPU;
1697
1698 public:
R600TargetInfo(const llvm::Triple & Triple)1699 R600TargetInfo(const llvm::Triple &Triple)
1700 : TargetInfo(Triple) {
1701
1702 if (Triple.getArch() == llvm::Triple::amdgcn) {
1703 DescriptionString = DescriptionStringSI;
1704 GPU = GK_SOUTHERN_ISLANDS;
1705 } else {
1706 DescriptionString = DescriptionStringR600;
1707 GPU = GK_R600;
1708 }
1709 AddrSpaceMap = &R600AddrSpaceMap;
1710 UseAddrSpaceMapMangling = true;
1711 }
1712
getPointerWidthV(unsigned AddrSpace) const1713 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1714 if (GPU <= GK_CAYMAN)
1715 return 32;
1716
1717 switch(AddrSpace) {
1718 default:
1719 return 64;
1720 case 0:
1721 case 3:
1722 case 5:
1723 return 32;
1724 }
1725 }
1726
getClobbers() const1727 const char * getClobbers() const override {
1728 return "";
1729 }
1730
1731 void getGCCRegNames(const char * const *&Names,
1732 unsigned &NumNames) const override;
1733
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const1734 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1735 unsigned &NumAliases) const override {
1736 Aliases = nullptr;
1737 NumAliases = 0;
1738 }
1739
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & info) const1740 bool validateAsmConstraint(const char *&Name,
1741 TargetInfo::ConstraintInfo &info) const override {
1742 return true;
1743 }
1744
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const1745 void getTargetBuiltins(const Builtin::Info *&Records,
1746 unsigned &NumRecords) const override {
1747 Records = BuiltinInfo;
1748 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1749 }
1750
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const1751 void getTargetDefines(const LangOptions &Opts,
1752 MacroBuilder &Builder) const override {
1753 Builder.defineMacro("__R600__");
1754 if (GPU >= GK_SOUTHERN_ISLANDS && Opts.OpenCL)
1755 Builder.defineMacro("cl_khr_fp64");
1756 }
1757
getBuiltinVaListKind() const1758 BuiltinVaListKind getBuiltinVaListKind() const override {
1759 return TargetInfo::CharPtrBuiltinVaList;
1760 }
1761
setCPU(const std::string & Name)1762 bool setCPU(const std::string &Name) override {
1763 GPU = llvm::StringSwitch<GPUKind>(Name)
1764 .Case("r600" , GK_R600)
1765 .Case("rv610", GK_R600)
1766 .Case("rv620", GK_R600)
1767 .Case("rv630", GK_R600)
1768 .Case("rv635", GK_R600)
1769 .Case("rs780", GK_R600)
1770 .Case("rs880", GK_R600)
1771 .Case("rv670", GK_R600_DOUBLE_OPS)
1772 .Case("rv710", GK_R700)
1773 .Case("rv730", GK_R700)
1774 .Case("rv740", GK_R700_DOUBLE_OPS)
1775 .Case("rv770", GK_R700_DOUBLE_OPS)
1776 .Case("palm", GK_EVERGREEN)
1777 .Case("cedar", GK_EVERGREEN)
1778 .Case("sumo", GK_EVERGREEN)
1779 .Case("sumo2", GK_EVERGREEN)
1780 .Case("redwood", GK_EVERGREEN)
1781 .Case("juniper", GK_EVERGREEN)
1782 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1783 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1784 .Case("barts", GK_NORTHERN_ISLANDS)
1785 .Case("turks", GK_NORTHERN_ISLANDS)
1786 .Case("caicos", GK_NORTHERN_ISLANDS)
1787 .Case("cayman", GK_CAYMAN)
1788 .Case("aruba", GK_CAYMAN)
1789 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1790 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1791 .Case("verde", GK_SOUTHERN_ISLANDS)
1792 .Case("oland", GK_SOUTHERN_ISLANDS)
1793 .Case("hainan", GK_SOUTHERN_ISLANDS)
1794 .Case("bonaire", GK_SEA_ISLANDS)
1795 .Case("kabini", GK_SEA_ISLANDS)
1796 .Case("kaveri", GK_SEA_ISLANDS)
1797 .Case("hawaii", GK_SEA_ISLANDS)
1798 .Case("mullins", GK_SEA_ISLANDS)
1799 .Default(GK_NONE);
1800
1801 if (GPU == GK_NONE) {
1802 return false;
1803 }
1804
1805 // Set the correct data layout
1806 switch (GPU) {
1807 case GK_NONE:
1808 case GK_R600:
1809 case GK_R700:
1810 case GK_EVERGREEN:
1811 case GK_NORTHERN_ISLANDS:
1812 DescriptionString = DescriptionStringR600;
1813 break;
1814 case GK_R600_DOUBLE_OPS:
1815 case GK_R700_DOUBLE_OPS:
1816 case GK_EVERGREEN_DOUBLE_OPS:
1817 case GK_CAYMAN:
1818 DescriptionString = DescriptionStringR600DoubleOps;
1819 break;
1820 case GK_SOUTHERN_ISLANDS:
1821 case GK_SEA_ISLANDS:
1822 DescriptionString = DescriptionStringSI;
1823 break;
1824 }
1825
1826 return true;
1827 }
1828 };
1829
1830 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1831 #define BUILTIN(ID, TYPE, ATTRS) \
1832 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1833 #include "clang/Basic/BuiltinsR600.def"
1834 };
1835 const char * const R600TargetInfo::GCCRegNames[] = {
1836 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1837 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1838 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1839 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1840 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
1841 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
1842 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
1843 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
1844 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
1845 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
1846 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
1847 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
1848 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
1849 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
1850 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
1851 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
1852 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
1853 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
1854 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
1855 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
1856 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
1857 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
1858 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
1859 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
1860 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
1861 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
1862 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
1863 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
1864 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
1865 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
1866 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
1867 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
1868 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1869 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
1870 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
1871 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1872 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
1873 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
1874 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
1875 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
1876 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
1877 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
1878 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
1879 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
1880 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
1881 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
1882 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
1883 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
1884 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
1885 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
1886 };
1887
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const1888 void R600TargetInfo::getGCCRegNames(const char * const *&Names,
1889 unsigned &NumNames) const {
1890 Names = GCCRegNames;
1891 NumNames = llvm::array_lengthof(GCCRegNames);
1892 }
1893
1894 // Namespace for x86 abstract base class
1895 const Builtin::Info BuiltinInfo[] = {
1896 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1897 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1898 ALL_LANGUAGES },
1899 #include "clang/Basic/BuiltinsX86.def"
1900 };
1901
1902 static const char* const GCCRegNames[] = {
1903 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1904 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1905 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1906 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1907 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1908 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1909 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1910 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1911 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1912 };
1913
1914 const TargetInfo::AddlRegName AddlRegNames[] = {
1915 { { "al", "ah", "eax", "rax" }, 0 },
1916 { { "bl", "bh", "ebx", "rbx" }, 3 },
1917 { { "cl", "ch", "ecx", "rcx" }, 2 },
1918 { { "dl", "dh", "edx", "rdx" }, 1 },
1919 { { "esi", "rsi" }, 4 },
1920 { { "edi", "rdi" }, 5 },
1921 { { "esp", "rsp" }, 7 },
1922 { { "ebp", "rbp" }, 6 },
1923 };
1924
1925 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1926 // most of the implementation can be shared.
1927 class X86TargetInfo : public TargetInfo {
1928 enum X86SSEEnum {
1929 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1930 } SSELevel;
1931 enum MMX3DNowEnum {
1932 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1933 } MMX3DNowLevel;
1934 enum XOPEnum {
1935 NoXOP,
1936 SSE4A,
1937 FMA4,
1938 XOP
1939 } XOPLevel;
1940
1941 bool HasAES;
1942 bool HasPCLMUL;
1943 bool HasLZCNT;
1944 bool HasRDRND;
1945 bool HasFSGSBASE;
1946 bool HasBMI;
1947 bool HasBMI2;
1948 bool HasPOPCNT;
1949 bool HasRTM;
1950 bool HasPRFCHW;
1951 bool HasRDSEED;
1952 bool HasADX;
1953 bool HasTBM;
1954 bool HasFMA;
1955 bool HasF16C;
1956 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1957 HasAVX512VL;
1958 bool HasSHA;
1959 bool HasCX16;
1960
1961 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1962 ///
1963 /// Each enumeration represents a particular CPU supported by Clang. These
1964 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1965 enum CPUKind {
1966 CK_Generic,
1967
1968 /// \name i386
1969 /// i386-generation processors.
1970 //@{
1971 CK_i386,
1972 //@}
1973
1974 /// \name i486
1975 /// i486-generation processors.
1976 //@{
1977 CK_i486,
1978 CK_WinChipC6,
1979 CK_WinChip2,
1980 CK_C3,
1981 //@}
1982
1983 /// \name i586
1984 /// i586-generation processors, P5 microarchitecture based.
1985 //@{
1986 CK_i586,
1987 CK_Pentium,
1988 CK_PentiumMMX,
1989 //@}
1990
1991 /// \name i686
1992 /// i686-generation processors, P6 / Pentium M microarchitecture based.
1993 //@{
1994 CK_i686,
1995 CK_PentiumPro,
1996 CK_Pentium2,
1997 CK_Pentium3,
1998 CK_Pentium3M,
1999 CK_PentiumM,
2000 CK_C3_2,
2001
2002 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2003 /// Clang however has some logic to suport this.
2004 // FIXME: Warn, deprecate, and potentially remove this.
2005 CK_Yonah,
2006 //@}
2007
2008 /// \name Netburst
2009 /// Netburst microarchitecture based processors.
2010 //@{
2011 CK_Pentium4,
2012 CK_Pentium4M,
2013 CK_Prescott,
2014 CK_Nocona,
2015 //@}
2016
2017 /// \name Core
2018 /// Core microarchitecture based processors.
2019 //@{
2020 CK_Core2,
2021
2022 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2023 /// codename which GCC no longer accepts as an option to -march, but Clang
2024 /// has some logic for recognizing it.
2025 // FIXME: Warn, deprecate, and potentially remove this.
2026 CK_Penryn,
2027 //@}
2028
2029 /// \name Atom
2030 /// Atom processors
2031 //@{
2032 CK_Bonnell,
2033 CK_Silvermont,
2034 //@}
2035
2036 /// \name Nehalem
2037 /// Nehalem microarchitecture based processors.
2038 CK_Nehalem,
2039
2040 /// \name Westmere
2041 /// Westmere microarchitecture based processors.
2042 CK_Westmere,
2043
2044 /// \name Sandy Bridge
2045 /// Sandy Bridge microarchitecture based processors.
2046 CK_SandyBridge,
2047
2048 /// \name Ivy Bridge
2049 /// Ivy Bridge microarchitecture based processors.
2050 CK_IvyBridge,
2051
2052 /// \name Haswell
2053 /// Haswell microarchitecture based processors.
2054 CK_Haswell,
2055
2056 /// \name Broadwell
2057 /// Broadwell microarchitecture based processors.
2058 CK_Broadwell,
2059
2060 /// \name Skylake
2061 /// Skylake microarchitecture based processors.
2062 CK_Skylake,
2063
2064 /// \name Knights Landing
2065 /// Knights Landing processor.
2066 CK_KNL,
2067
2068 /// \name K6
2069 /// K6 architecture processors.
2070 //@{
2071 CK_K6,
2072 CK_K6_2,
2073 CK_K6_3,
2074 //@}
2075
2076 /// \name K7
2077 /// K7 architecture processors.
2078 //@{
2079 CK_Athlon,
2080 CK_AthlonThunderbird,
2081 CK_Athlon4,
2082 CK_AthlonXP,
2083 CK_AthlonMP,
2084 //@}
2085
2086 /// \name K8
2087 /// K8 architecture processors.
2088 //@{
2089 CK_Athlon64,
2090 CK_Athlon64SSE3,
2091 CK_AthlonFX,
2092 CK_K8,
2093 CK_K8SSE3,
2094 CK_Opteron,
2095 CK_OpteronSSE3,
2096 CK_AMDFAM10,
2097 //@}
2098
2099 /// \name Bobcat
2100 /// Bobcat architecture processors.
2101 //@{
2102 CK_BTVER1,
2103 CK_BTVER2,
2104 //@}
2105
2106 /// \name Bulldozer
2107 /// Bulldozer architecture processors.
2108 //@{
2109 CK_BDVER1,
2110 CK_BDVER2,
2111 CK_BDVER3,
2112 CK_BDVER4,
2113 //@}
2114
2115 /// This specification is deprecated and will be removed in the future.
2116 /// Users should prefer \see CK_K8.
2117 // FIXME: Warn on this when the CPU is set to it.
2118 //@{
2119 CK_x86_64,
2120 //@}
2121
2122 /// \name Geode
2123 /// Geode processors.
2124 //@{
2125 CK_Geode
2126 //@}
2127 } CPU;
2128
2129 enum FPMathKind {
2130 FP_Default,
2131 FP_SSE,
2132 FP_387
2133 } FPMath;
2134
2135 public:
X86TargetInfo(const llvm::Triple & Triple)2136 X86TargetInfo(const llvm::Triple &Triple)
2137 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
2138 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
2139 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
2140 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
2141 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
2142 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
2143 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
2144 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
2145 BigEndian = false;
2146 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2147 }
getFloatEvalMethod() const2148 unsigned getFloatEvalMethod() const override {
2149 // X87 evaluates with 80 bits "long double" precision.
2150 return SSELevel == NoSSE ? 2 : 0;
2151 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const2152 void getTargetBuiltins(const Builtin::Info *&Records,
2153 unsigned &NumRecords) const override {
2154 Records = BuiltinInfo;
2155 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
2156 }
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const2157 void getGCCRegNames(const char * const *&Names,
2158 unsigned &NumNames) const override {
2159 Names = GCCRegNames;
2160 NumNames = llvm::array_lengthof(GCCRegNames);
2161 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const2162 void getGCCRegAliases(const GCCRegAlias *&Aliases,
2163 unsigned &NumAliases) const override {
2164 Aliases = nullptr;
2165 NumAliases = 0;
2166 }
getGCCAddlRegNames(const AddlRegName * & Names,unsigned & NumNames) const2167 void getGCCAddlRegNames(const AddlRegName *&Names,
2168 unsigned &NumNames) const override {
2169 Names = AddlRegNames;
2170 NumNames = llvm::array_lengthof(AddlRegNames);
2171 }
2172 bool validateAsmConstraint(const char *&Name,
2173 TargetInfo::ConstraintInfo &info) const override;
2174
2175 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2176
2177 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2178
2179 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2180
2181 std::string convertConstraint(const char *&Constraint) const override;
getClobbers() const2182 const char *getClobbers() const override {
2183 return "~{dirflag},~{fpsr},~{flags}";
2184 }
2185 void getTargetDefines(const LangOptions &Opts,
2186 MacroBuilder &Builder) const override;
2187 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2188 bool Enabled);
2189 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2190 bool Enabled);
2191 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2192 bool Enabled);
setFeatureEnabled(llvm::StringMap<bool> & Features,StringRef Name,bool Enabled) const2193 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2194 StringRef Name, bool Enabled) const override {
2195 setFeatureEnabledImpl(Features, Name, Enabled);
2196 }
2197 // This exists purely to cut down on the number of virtual calls in
2198 // getDefaultFeatures which calls this repeatedly.
2199 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2200 StringRef Name, bool Enabled);
2201 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2202 bool hasFeature(StringRef Feature) const override;
2203 bool handleTargetFeatures(std::vector<std::string> &Features,
2204 DiagnosticsEngine &Diags) override;
getABI() const2205 StringRef getABI() const override {
2206 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2207 return "avx";
2208 else if (getTriple().getArch() == llvm::Triple::x86 &&
2209 MMX3DNowLevel == NoMMX3DNow)
2210 return "no-mmx";
2211 return "";
2212 }
setCPU(const std::string & Name)2213 bool setCPU(const std::string &Name) override {
2214 CPU = llvm::StringSwitch<CPUKind>(Name)
2215 .Case("i386", CK_i386)
2216 .Case("i486", CK_i486)
2217 .Case("winchip-c6", CK_WinChipC6)
2218 .Case("winchip2", CK_WinChip2)
2219 .Case("c3", CK_C3)
2220 .Case("i586", CK_i586)
2221 .Case("pentium", CK_Pentium)
2222 .Case("pentium-mmx", CK_PentiumMMX)
2223 .Case("i686", CK_i686)
2224 .Case("pentiumpro", CK_PentiumPro)
2225 .Case("pentium2", CK_Pentium2)
2226 .Case("pentium3", CK_Pentium3)
2227 .Case("pentium3m", CK_Pentium3M)
2228 .Case("pentium-m", CK_PentiumM)
2229 .Case("c3-2", CK_C3_2)
2230 .Case("yonah", CK_Yonah)
2231 .Case("pentium4", CK_Pentium4)
2232 .Case("pentium4m", CK_Pentium4M)
2233 .Case("prescott", CK_Prescott)
2234 .Case("nocona", CK_Nocona)
2235 .Case("core2", CK_Core2)
2236 .Case("penryn", CK_Penryn)
2237 .Case("bonnell", CK_Bonnell)
2238 .Case("atom", CK_Bonnell) // Legacy name.
2239 .Case("silvermont", CK_Silvermont)
2240 .Case("slm", CK_Silvermont) // Legacy name.
2241 .Case("nehalem", CK_Nehalem)
2242 .Case("corei7", CK_Nehalem) // Legacy name.
2243 .Case("westmere", CK_Westmere)
2244 .Case("sandybridge", CK_SandyBridge)
2245 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2246 .Case("ivybridge", CK_IvyBridge)
2247 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2248 .Case("haswell", CK_Haswell)
2249 .Case("core-avx2", CK_Haswell) // Legacy name.
2250 .Case("broadwell", CK_Broadwell)
2251 .Case("skylake", CK_Skylake)
2252 .Case("skx", CK_Skylake) // Legacy name.
2253 .Case("knl", CK_KNL)
2254 .Case("k6", CK_K6)
2255 .Case("k6-2", CK_K6_2)
2256 .Case("k6-3", CK_K6_3)
2257 .Case("athlon", CK_Athlon)
2258 .Case("athlon-tbird", CK_AthlonThunderbird)
2259 .Case("athlon-4", CK_Athlon4)
2260 .Case("athlon-xp", CK_AthlonXP)
2261 .Case("athlon-mp", CK_AthlonMP)
2262 .Case("athlon64", CK_Athlon64)
2263 .Case("athlon64-sse3", CK_Athlon64SSE3)
2264 .Case("athlon-fx", CK_AthlonFX)
2265 .Case("k8", CK_K8)
2266 .Case("k8-sse3", CK_K8SSE3)
2267 .Case("opteron", CK_Opteron)
2268 .Case("opteron-sse3", CK_OpteronSSE3)
2269 .Case("barcelona", CK_AMDFAM10)
2270 .Case("amdfam10", CK_AMDFAM10)
2271 .Case("btver1", CK_BTVER1)
2272 .Case("btver2", CK_BTVER2)
2273 .Case("bdver1", CK_BDVER1)
2274 .Case("bdver2", CK_BDVER2)
2275 .Case("bdver3", CK_BDVER3)
2276 .Case("bdver4", CK_BDVER4)
2277 .Case("x86-64", CK_x86_64)
2278 .Case("geode", CK_Geode)
2279 .Default(CK_Generic);
2280
2281 // Perform any per-CPU checks necessary to determine if this CPU is
2282 // acceptable.
2283 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2284 // invalid without explaining *why*.
2285 switch (CPU) {
2286 case CK_Generic:
2287 // No processor selected!
2288 return false;
2289
2290 case CK_i386:
2291 case CK_i486:
2292 case CK_WinChipC6:
2293 case CK_WinChip2:
2294 case CK_C3:
2295 case CK_i586:
2296 case CK_Pentium:
2297 case CK_PentiumMMX:
2298 case CK_i686:
2299 case CK_PentiumPro:
2300 case CK_Pentium2:
2301 case CK_Pentium3:
2302 case CK_Pentium3M:
2303 case CK_PentiumM:
2304 case CK_Yonah:
2305 case CK_C3_2:
2306 case CK_Pentium4:
2307 case CK_Pentium4M:
2308 case CK_Prescott:
2309 case CK_K6:
2310 case CK_K6_2:
2311 case CK_K6_3:
2312 case CK_Athlon:
2313 case CK_AthlonThunderbird:
2314 case CK_Athlon4:
2315 case CK_AthlonXP:
2316 case CK_AthlonMP:
2317 case CK_Geode:
2318 // Only accept certain architectures when compiling in 32-bit mode.
2319 if (getTriple().getArch() != llvm::Triple::x86)
2320 return false;
2321
2322 // Fallthrough
2323 case CK_Nocona:
2324 case CK_Core2:
2325 case CK_Penryn:
2326 case CK_Bonnell:
2327 case CK_Silvermont:
2328 case CK_Nehalem:
2329 case CK_Westmere:
2330 case CK_SandyBridge:
2331 case CK_IvyBridge:
2332 case CK_Haswell:
2333 case CK_Broadwell:
2334 case CK_Skylake:
2335 case CK_KNL:
2336 case CK_Athlon64:
2337 case CK_Athlon64SSE3:
2338 case CK_AthlonFX:
2339 case CK_K8:
2340 case CK_K8SSE3:
2341 case CK_Opteron:
2342 case CK_OpteronSSE3:
2343 case CK_AMDFAM10:
2344 case CK_BTVER1:
2345 case CK_BTVER2:
2346 case CK_BDVER1:
2347 case CK_BDVER2:
2348 case CK_BDVER3:
2349 case CK_BDVER4:
2350 case CK_x86_64:
2351 return true;
2352 }
2353 llvm_unreachable("Unhandled CPU kind");
2354 }
2355
2356 bool setFPMath(StringRef Name) override;
2357
checkCallingConvention(CallingConv CC) const2358 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2359 // We accept all non-ARM calling conventions
2360 return (CC == CC_X86ThisCall ||
2361 CC == CC_X86FastCall ||
2362 CC == CC_X86StdCall ||
2363 CC == CC_X86VectorCall ||
2364 CC == CC_C ||
2365 CC == CC_X86Pascal ||
2366 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2367 }
2368
getDefaultCallingConv(CallingConvMethodType MT) const2369 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2370 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2371 }
2372
hasSjLjLowering() const2373 bool hasSjLjLowering() const override {
2374 return true;
2375 }
2376 };
2377
setFPMath(StringRef Name)2378 bool X86TargetInfo::setFPMath(StringRef Name) {
2379 if (Name == "387") {
2380 FPMath = FP_387;
2381 return true;
2382 }
2383 if (Name == "sse") {
2384 FPMath = FP_SSE;
2385 return true;
2386 }
2387 return false;
2388 }
2389
getDefaultFeatures(llvm::StringMap<bool> & Features) const2390 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2391 // FIXME: This *really* should not be here.
2392
2393 // X86_64 always has SSE2.
2394 if (getTriple().getArch() == llvm::Triple::x86_64)
2395 setFeatureEnabledImpl(Features, "sse2", true);
2396
2397 switch (CPU) {
2398 case CK_Generic:
2399 case CK_i386:
2400 case CK_i486:
2401 case CK_i586:
2402 case CK_Pentium:
2403 case CK_i686:
2404 case CK_PentiumPro:
2405 break;
2406 case CK_PentiumMMX:
2407 case CK_Pentium2:
2408 case CK_K6:
2409 case CK_WinChipC6:
2410 setFeatureEnabledImpl(Features, "mmx", true);
2411 break;
2412 case CK_Pentium3:
2413 case CK_Pentium3M:
2414 case CK_C3_2:
2415 setFeatureEnabledImpl(Features, "sse", true);
2416 break;
2417 case CK_PentiumM:
2418 case CK_Pentium4:
2419 case CK_Pentium4M:
2420 case CK_x86_64:
2421 setFeatureEnabledImpl(Features, "sse2", true);
2422 break;
2423 case CK_Yonah:
2424 case CK_Prescott:
2425 case CK_Nocona:
2426 setFeatureEnabledImpl(Features, "sse3", true);
2427 setFeatureEnabledImpl(Features, "cx16", true);
2428 break;
2429 case CK_Core2:
2430 case CK_Bonnell:
2431 setFeatureEnabledImpl(Features, "ssse3", true);
2432 setFeatureEnabledImpl(Features, "cx16", true);
2433 break;
2434 case CK_Penryn:
2435 setFeatureEnabledImpl(Features, "sse4.1", true);
2436 setFeatureEnabledImpl(Features, "cx16", true);
2437 break;
2438 case CK_Skylake:
2439 setFeatureEnabledImpl(Features, "avx512f", true);
2440 setFeatureEnabledImpl(Features, "avx512cd", true);
2441 setFeatureEnabledImpl(Features, "avx512dq", true);
2442 setFeatureEnabledImpl(Features, "avx512bw", true);
2443 setFeatureEnabledImpl(Features, "avx512vl", true);
2444 // FALLTHROUGH
2445 case CK_Broadwell:
2446 setFeatureEnabledImpl(Features, "rdseed", true);
2447 setFeatureEnabledImpl(Features, "adx", true);
2448 // FALLTHROUGH
2449 case CK_Haswell:
2450 setFeatureEnabledImpl(Features, "avx2", true);
2451 setFeatureEnabledImpl(Features, "lzcnt", true);
2452 setFeatureEnabledImpl(Features, "bmi", true);
2453 setFeatureEnabledImpl(Features, "bmi2", true);
2454 setFeatureEnabledImpl(Features, "rtm", true);
2455 setFeatureEnabledImpl(Features, "fma", true);
2456 // FALLTHROUGH
2457 case CK_IvyBridge:
2458 setFeatureEnabledImpl(Features, "rdrnd", true);
2459 setFeatureEnabledImpl(Features, "f16c", true);
2460 setFeatureEnabledImpl(Features, "fsgsbase", true);
2461 // FALLTHROUGH
2462 case CK_SandyBridge:
2463 setFeatureEnabledImpl(Features, "avx", true);
2464 // FALLTHROUGH
2465 case CK_Westmere:
2466 case CK_Silvermont:
2467 setFeatureEnabledImpl(Features, "aes", true);
2468 setFeatureEnabledImpl(Features, "pclmul", true);
2469 // FALLTHROUGH
2470 case CK_Nehalem:
2471 setFeatureEnabledImpl(Features, "sse4.2", true);
2472 setFeatureEnabledImpl(Features, "cx16", true);
2473 break;
2474 case CK_KNL:
2475 setFeatureEnabledImpl(Features, "avx512f", true);
2476 setFeatureEnabledImpl(Features, "avx512cd", true);
2477 setFeatureEnabledImpl(Features, "avx512er", true);
2478 setFeatureEnabledImpl(Features, "avx512pf", true);
2479 setFeatureEnabledImpl(Features, "rdseed", true);
2480 setFeatureEnabledImpl(Features, "adx", true);
2481 setFeatureEnabledImpl(Features, "lzcnt", true);
2482 setFeatureEnabledImpl(Features, "bmi", true);
2483 setFeatureEnabledImpl(Features, "bmi2", true);
2484 setFeatureEnabledImpl(Features, "rtm", true);
2485 setFeatureEnabledImpl(Features, "fma", true);
2486 setFeatureEnabledImpl(Features, "rdrnd", true);
2487 setFeatureEnabledImpl(Features, "f16c", true);
2488 setFeatureEnabledImpl(Features, "fsgsbase", true);
2489 setFeatureEnabledImpl(Features, "aes", true);
2490 setFeatureEnabledImpl(Features, "pclmul", true);
2491 setFeatureEnabledImpl(Features, "cx16", true);
2492 break;
2493 case CK_K6_2:
2494 case CK_K6_3:
2495 case CK_WinChip2:
2496 case CK_C3:
2497 setFeatureEnabledImpl(Features, "3dnow", true);
2498 break;
2499 case CK_Athlon:
2500 case CK_AthlonThunderbird:
2501 case CK_Geode:
2502 setFeatureEnabledImpl(Features, "3dnowa", true);
2503 break;
2504 case CK_Athlon4:
2505 case CK_AthlonXP:
2506 case CK_AthlonMP:
2507 setFeatureEnabledImpl(Features, "sse", true);
2508 setFeatureEnabledImpl(Features, "3dnowa", true);
2509 break;
2510 case CK_K8:
2511 case CK_Opteron:
2512 case CK_Athlon64:
2513 case CK_AthlonFX:
2514 setFeatureEnabledImpl(Features, "sse2", true);
2515 setFeatureEnabledImpl(Features, "3dnowa", true);
2516 break;
2517 case CK_AMDFAM10:
2518 setFeatureEnabledImpl(Features, "sse4a", true);
2519 setFeatureEnabledImpl(Features, "lzcnt", true);
2520 setFeatureEnabledImpl(Features, "popcnt", true);
2521 // FALLTHROUGH
2522 case CK_K8SSE3:
2523 case CK_OpteronSSE3:
2524 case CK_Athlon64SSE3:
2525 setFeatureEnabledImpl(Features, "sse3", true);
2526 setFeatureEnabledImpl(Features, "3dnowa", true);
2527 break;
2528 case CK_BTVER2:
2529 setFeatureEnabledImpl(Features, "avx", true);
2530 setFeatureEnabledImpl(Features, "aes", true);
2531 setFeatureEnabledImpl(Features, "pclmul", true);
2532 setFeatureEnabledImpl(Features, "bmi", true);
2533 setFeatureEnabledImpl(Features, "f16c", true);
2534 // FALLTHROUGH
2535 case CK_BTVER1:
2536 setFeatureEnabledImpl(Features, "ssse3", true);
2537 setFeatureEnabledImpl(Features, "sse4a", true);
2538 setFeatureEnabledImpl(Features, "lzcnt", true);
2539 setFeatureEnabledImpl(Features, "popcnt", true);
2540 setFeatureEnabledImpl(Features, "prfchw", true);
2541 setFeatureEnabledImpl(Features, "cx16", true);
2542 break;
2543 case CK_BDVER4:
2544 setFeatureEnabledImpl(Features, "avx2", true);
2545 setFeatureEnabledImpl(Features, "bmi2", true);
2546 // FALLTHROUGH
2547 case CK_BDVER3:
2548 setFeatureEnabledImpl(Features, "fsgsbase", true);
2549 // FALLTHROUGH
2550 case CK_BDVER2:
2551 setFeatureEnabledImpl(Features, "bmi", true);
2552 setFeatureEnabledImpl(Features, "fma", true);
2553 setFeatureEnabledImpl(Features, "f16c", true);
2554 setFeatureEnabledImpl(Features, "tbm", true);
2555 // FALLTHROUGH
2556 case CK_BDVER1:
2557 // xop implies avx, sse4a and fma4.
2558 setFeatureEnabledImpl(Features, "xop", true);
2559 setFeatureEnabledImpl(Features, "lzcnt", true);
2560 setFeatureEnabledImpl(Features, "aes", true);
2561 setFeatureEnabledImpl(Features, "pclmul", true);
2562 setFeatureEnabledImpl(Features, "prfchw", true);
2563 setFeatureEnabledImpl(Features, "cx16", true);
2564 break;
2565 }
2566 }
2567
setSSELevel(llvm::StringMap<bool> & Features,X86SSEEnum Level,bool Enabled)2568 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2569 X86SSEEnum Level, bool Enabled) {
2570 if (Enabled) {
2571 switch (Level) {
2572 case AVX512F:
2573 Features["avx512f"] = true;
2574 case AVX2:
2575 Features["avx2"] = true;
2576 case AVX:
2577 Features["avx"] = true;
2578 case SSE42:
2579 Features["sse4.2"] = true;
2580 case SSE41:
2581 Features["sse4.1"] = true;
2582 case SSSE3:
2583 Features["ssse3"] = true;
2584 case SSE3:
2585 Features["sse3"] = true;
2586 case SSE2:
2587 Features["sse2"] = true;
2588 case SSE1:
2589 Features["sse"] = true;
2590 case NoSSE:
2591 break;
2592 }
2593 return;
2594 }
2595
2596 switch (Level) {
2597 case NoSSE:
2598 case SSE1:
2599 Features["sse"] = false;
2600 case SSE2:
2601 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2602 Features["sha"] = false;
2603 case SSE3:
2604 Features["sse3"] = false;
2605 setXOPLevel(Features, NoXOP, false);
2606 case SSSE3:
2607 Features["ssse3"] = false;
2608 case SSE41:
2609 Features["sse4.1"] = false;
2610 case SSE42:
2611 Features["sse4.2"] = false;
2612 case AVX:
2613 Features["fma"] = Features["avx"] = Features["f16c"] = false;
2614 setXOPLevel(Features, FMA4, false);
2615 case AVX2:
2616 Features["avx2"] = false;
2617 case AVX512F:
2618 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2619 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2620 Features["avx512vl"] = false;
2621 }
2622 }
2623
setMMXLevel(llvm::StringMap<bool> & Features,MMX3DNowEnum Level,bool Enabled)2624 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2625 MMX3DNowEnum Level, bool Enabled) {
2626 if (Enabled) {
2627 switch (Level) {
2628 case AMD3DNowAthlon:
2629 Features["3dnowa"] = true;
2630 case AMD3DNow:
2631 Features["3dnow"] = true;
2632 case MMX:
2633 Features["mmx"] = true;
2634 case NoMMX3DNow:
2635 break;
2636 }
2637 return;
2638 }
2639
2640 switch (Level) {
2641 case NoMMX3DNow:
2642 case MMX:
2643 Features["mmx"] = false;
2644 case AMD3DNow:
2645 Features["3dnow"] = false;
2646 case AMD3DNowAthlon:
2647 Features["3dnowa"] = false;
2648 }
2649 }
2650
setXOPLevel(llvm::StringMap<bool> & Features,XOPEnum Level,bool Enabled)2651 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2652 bool Enabled) {
2653 if (Enabled) {
2654 switch (Level) {
2655 case XOP:
2656 Features["xop"] = true;
2657 case FMA4:
2658 Features["fma4"] = true;
2659 setSSELevel(Features, AVX, true);
2660 case SSE4A:
2661 Features["sse4a"] = true;
2662 setSSELevel(Features, SSE3, true);
2663 case NoXOP:
2664 break;
2665 }
2666 return;
2667 }
2668
2669 switch (Level) {
2670 case NoXOP:
2671 case SSE4A:
2672 Features["sse4a"] = false;
2673 case FMA4:
2674 Features["fma4"] = false;
2675 case XOP:
2676 Features["xop"] = false;
2677 }
2678 }
2679
setFeatureEnabledImpl(llvm::StringMap<bool> & Features,StringRef Name,bool Enabled)2680 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2681 StringRef Name, bool Enabled) {
2682 Features[Name] = Enabled;
2683
2684 if (Name == "mmx") {
2685 setMMXLevel(Features, MMX, Enabled);
2686 } else if (Name == "sse") {
2687 setSSELevel(Features, SSE1, Enabled);
2688 } else if (Name == "sse2") {
2689 setSSELevel(Features, SSE2, Enabled);
2690 } else if (Name == "sse3") {
2691 setSSELevel(Features, SSE3, Enabled);
2692 } else if (Name == "ssse3") {
2693 setSSELevel(Features, SSSE3, Enabled);
2694 } else if (Name == "sse4.2") {
2695 setSSELevel(Features, SSE42, Enabled);
2696 } else if (Name == "sse4.1") {
2697 setSSELevel(Features, SSE41, Enabled);
2698 } else if (Name == "3dnow") {
2699 setMMXLevel(Features, AMD3DNow, Enabled);
2700 } else if (Name == "3dnowa") {
2701 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2702 } else if (Name == "aes") {
2703 if (Enabled)
2704 setSSELevel(Features, SSE2, Enabled);
2705 } else if (Name == "pclmul") {
2706 if (Enabled)
2707 setSSELevel(Features, SSE2, Enabled);
2708 } else if (Name == "avx") {
2709 setSSELevel(Features, AVX, Enabled);
2710 } else if (Name == "avx2") {
2711 setSSELevel(Features, AVX2, Enabled);
2712 } else if (Name == "avx512f") {
2713 setSSELevel(Features, AVX512F, Enabled);
2714 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2715 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2716 if (Enabled)
2717 setSSELevel(Features, AVX512F, Enabled);
2718 } else if (Name == "fma") {
2719 if (Enabled)
2720 setSSELevel(Features, AVX, Enabled);
2721 } else if (Name == "fma4") {
2722 setXOPLevel(Features, FMA4, Enabled);
2723 } else if (Name == "xop") {
2724 setXOPLevel(Features, XOP, Enabled);
2725 } else if (Name == "sse4a") {
2726 setXOPLevel(Features, SSE4A, Enabled);
2727 } else if (Name == "f16c") {
2728 if (Enabled)
2729 setSSELevel(Features, AVX, Enabled);
2730 } else if (Name == "sha") {
2731 if (Enabled)
2732 setSSELevel(Features, SSE2, Enabled);
2733 }
2734 }
2735
2736 /// handleTargetFeatures - Perform initialization based on the user
2737 /// configured set of features.
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)2738 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2739 DiagnosticsEngine &Diags) {
2740 // Remember the maximum enabled sselevel.
2741 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2742 // Ignore disabled features.
2743 if (Features[i][0] == '-')
2744 continue;
2745
2746 StringRef Feature = StringRef(Features[i]).substr(1);
2747
2748 if (Feature == "aes") {
2749 HasAES = true;
2750 continue;
2751 }
2752
2753 if (Feature == "pclmul") {
2754 HasPCLMUL = true;
2755 continue;
2756 }
2757
2758 if (Feature == "lzcnt") {
2759 HasLZCNT = true;
2760 continue;
2761 }
2762
2763 if (Feature == "rdrnd") {
2764 HasRDRND = true;
2765 continue;
2766 }
2767
2768 if (Feature == "fsgsbase") {
2769 HasFSGSBASE = true;
2770 continue;
2771 }
2772
2773 if (Feature == "bmi") {
2774 HasBMI = true;
2775 continue;
2776 }
2777
2778 if (Feature == "bmi2") {
2779 HasBMI2 = true;
2780 continue;
2781 }
2782
2783 if (Feature == "popcnt") {
2784 HasPOPCNT = true;
2785 continue;
2786 }
2787
2788 if (Feature == "rtm") {
2789 HasRTM = true;
2790 continue;
2791 }
2792
2793 if (Feature == "prfchw") {
2794 HasPRFCHW = true;
2795 continue;
2796 }
2797
2798 if (Feature == "rdseed") {
2799 HasRDSEED = true;
2800 continue;
2801 }
2802
2803 if (Feature == "adx") {
2804 HasADX = true;
2805 continue;
2806 }
2807
2808 if (Feature == "tbm") {
2809 HasTBM = true;
2810 continue;
2811 }
2812
2813 if (Feature == "fma") {
2814 HasFMA = true;
2815 continue;
2816 }
2817
2818 if (Feature == "f16c") {
2819 HasF16C = true;
2820 continue;
2821 }
2822
2823 if (Feature == "avx512cd") {
2824 HasAVX512CD = true;
2825 continue;
2826 }
2827
2828 if (Feature == "avx512er") {
2829 HasAVX512ER = true;
2830 continue;
2831 }
2832
2833 if (Feature == "avx512pf") {
2834 HasAVX512PF = true;
2835 continue;
2836 }
2837
2838 if (Feature == "avx512dq") {
2839 HasAVX512DQ = true;
2840 continue;
2841 }
2842
2843 if (Feature == "avx512bw") {
2844 HasAVX512BW = true;
2845 continue;
2846 }
2847
2848 if (Feature == "avx512vl") {
2849 HasAVX512VL = true;
2850 continue;
2851 }
2852
2853 if (Feature == "sha") {
2854 HasSHA = true;
2855 continue;
2856 }
2857
2858 if (Feature == "cx16") {
2859 HasCX16 = true;
2860 continue;
2861 }
2862
2863 assert(Features[i][0] == '+' && "Invalid target feature!");
2864 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2865 .Case("avx512f", AVX512F)
2866 .Case("avx2", AVX2)
2867 .Case("avx", AVX)
2868 .Case("sse4.2", SSE42)
2869 .Case("sse4.1", SSE41)
2870 .Case("ssse3", SSSE3)
2871 .Case("sse3", SSE3)
2872 .Case("sse2", SSE2)
2873 .Case("sse", SSE1)
2874 .Default(NoSSE);
2875 SSELevel = std::max(SSELevel, Level);
2876
2877 MMX3DNowEnum ThreeDNowLevel =
2878 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2879 .Case("3dnowa", AMD3DNowAthlon)
2880 .Case("3dnow", AMD3DNow)
2881 .Case("mmx", MMX)
2882 .Default(NoMMX3DNow);
2883 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2884
2885 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2886 .Case("xop", XOP)
2887 .Case("fma4", FMA4)
2888 .Case("sse4a", SSE4A)
2889 .Default(NoXOP);
2890 XOPLevel = std::max(XOPLevel, XLevel);
2891 }
2892
2893 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2894 // Can't do this earlier because we need to be able to explicitly enable
2895 // popcnt and still disable sse4.2.
2896 if (!HasPOPCNT && SSELevel >= SSE42 &&
2897 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2898 HasPOPCNT = true;
2899 Features.push_back("+popcnt");
2900 }
2901
2902 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2903 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2904 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2905 HasPRFCHW = true;
2906 Features.push_back("+prfchw");
2907 }
2908
2909 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2910 // matches the selected sse level.
2911 if (FPMath == FP_SSE && SSELevel < SSE1) {
2912 Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2913 return false;
2914 } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2915 Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2916 return false;
2917 }
2918
2919 // Don't tell the backend if we're turning off mmx; it will end up disabling
2920 // SSE, which we don't want.
2921 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2922 // then enable MMX.
2923 std::vector<std::string>::iterator it;
2924 it = std::find(Features.begin(), Features.end(), "-mmx");
2925 if (it != Features.end())
2926 Features.erase(it);
2927 else if (SSELevel > NoSSE)
2928 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2929 return true;
2930 }
2931
2932 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2933 /// definitions for this particular subtarget.
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const2934 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2935 MacroBuilder &Builder) const {
2936 // Target identification.
2937 if (getTriple().getArch() == llvm::Triple::x86_64) {
2938 Builder.defineMacro("__amd64__");
2939 Builder.defineMacro("__amd64");
2940 Builder.defineMacro("__x86_64");
2941 Builder.defineMacro("__x86_64__");
2942 if (getTriple().getArchName() == "x86_64h") {
2943 Builder.defineMacro("__x86_64h");
2944 Builder.defineMacro("__x86_64h__");
2945 }
2946 } else {
2947 DefineStd(Builder, "i386", Opts);
2948 }
2949
2950 // Subtarget options.
2951 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2952 // truly should be based on -mtune options.
2953 switch (CPU) {
2954 case CK_Generic:
2955 break;
2956 case CK_i386:
2957 // The rest are coming from the i386 define above.
2958 Builder.defineMacro("__tune_i386__");
2959 break;
2960 case CK_i486:
2961 case CK_WinChipC6:
2962 case CK_WinChip2:
2963 case CK_C3:
2964 defineCPUMacros(Builder, "i486");
2965 break;
2966 case CK_PentiumMMX:
2967 Builder.defineMacro("__pentium_mmx__");
2968 Builder.defineMacro("__tune_pentium_mmx__");
2969 // Fallthrough
2970 case CK_i586:
2971 case CK_Pentium:
2972 defineCPUMacros(Builder, "i586");
2973 defineCPUMacros(Builder, "pentium");
2974 break;
2975 case CK_Pentium3:
2976 case CK_Pentium3M:
2977 case CK_PentiumM:
2978 Builder.defineMacro("__tune_pentium3__");
2979 // Fallthrough
2980 case CK_Pentium2:
2981 case CK_C3_2:
2982 Builder.defineMacro("__tune_pentium2__");
2983 // Fallthrough
2984 case CK_PentiumPro:
2985 Builder.defineMacro("__tune_i686__");
2986 Builder.defineMacro("__tune_pentiumpro__");
2987 // Fallthrough
2988 case CK_i686:
2989 Builder.defineMacro("__i686");
2990 Builder.defineMacro("__i686__");
2991 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2992 Builder.defineMacro("__pentiumpro");
2993 Builder.defineMacro("__pentiumpro__");
2994 break;
2995 case CK_Pentium4:
2996 case CK_Pentium4M:
2997 defineCPUMacros(Builder, "pentium4");
2998 break;
2999 case CK_Yonah:
3000 case CK_Prescott:
3001 case CK_Nocona:
3002 defineCPUMacros(Builder, "nocona");
3003 break;
3004 case CK_Core2:
3005 case CK_Penryn:
3006 defineCPUMacros(Builder, "core2");
3007 break;
3008 case CK_Bonnell:
3009 defineCPUMacros(Builder, "atom");
3010 break;
3011 case CK_Silvermont:
3012 defineCPUMacros(Builder, "slm");
3013 break;
3014 case CK_Nehalem:
3015 case CK_Westmere:
3016 case CK_SandyBridge:
3017 case CK_IvyBridge:
3018 case CK_Haswell:
3019 case CK_Broadwell:
3020 // FIXME: Historically, we defined this legacy name, it would be nice to
3021 // remove it at some point. We've never exposed fine-grained names for
3022 // recent primary x86 CPUs, and we should keep it that way.
3023 defineCPUMacros(Builder, "corei7");
3024 break;
3025 case CK_Skylake:
3026 // FIXME: Historically, we defined this legacy name, it would be nice to
3027 // remove it at some point. This is the only fine-grained CPU macro in the
3028 // main intel CPU line, and it would be better to not have these and force
3029 // people to use ISA macros.
3030 defineCPUMacros(Builder, "skx");
3031 break;
3032 case CK_KNL:
3033 defineCPUMacros(Builder, "knl");
3034 break;
3035 case CK_K6_2:
3036 Builder.defineMacro("__k6_2__");
3037 Builder.defineMacro("__tune_k6_2__");
3038 // Fallthrough
3039 case CK_K6_3:
3040 if (CPU != CK_K6_2) { // In case of fallthrough
3041 // FIXME: GCC may be enabling these in cases where some other k6
3042 // architecture is specified but -m3dnow is explicitly provided. The
3043 // exact semantics need to be determined and emulated here.
3044 Builder.defineMacro("__k6_3__");
3045 Builder.defineMacro("__tune_k6_3__");
3046 }
3047 // Fallthrough
3048 case CK_K6:
3049 defineCPUMacros(Builder, "k6");
3050 break;
3051 case CK_Athlon:
3052 case CK_AthlonThunderbird:
3053 case CK_Athlon4:
3054 case CK_AthlonXP:
3055 case CK_AthlonMP:
3056 defineCPUMacros(Builder, "athlon");
3057 if (SSELevel != NoSSE) {
3058 Builder.defineMacro("__athlon_sse__");
3059 Builder.defineMacro("__tune_athlon_sse__");
3060 }
3061 break;
3062 case CK_K8:
3063 case CK_K8SSE3:
3064 case CK_x86_64:
3065 case CK_Opteron:
3066 case CK_OpteronSSE3:
3067 case CK_Athlon64:
3068 case CK_Athlon64SSE3:
3069 case CK_AthlonFX:
3070 defineCPUMacros(Builder, "k8");
3071 break;
3072 case CK_AMDFAM10:
3073 defineCPUMacros(Builder, "amdfam10");
3074 break;
3075 case CK_BTVER1:
3076 defineCPUMacros(Builder, "btver1");
3077 break;
3078 case CK_BTVER2:
3079 defineCPUMacros(Builder, "btver2");
3080 break;
3081 case CK_BDVER1:
3082 defineCPUMacros(Builder, "bdver1");
3083 break;
3084 case CK_BDVER2:
3085 defineCPUMacros(Builder, "bdver2");
3086 break;
3087 case CK_BDVER3:
3088 defineCPUMacros(Builder, "bdver3");
3089 break;
3090 case CK_BDVER4:
3091 defineCPUMacros(Builder, "bdver4");
3092 break;
3093 case CK_Geode:
3094 defineCPUMacros(Builder, "geode");
3095 break;
3096 }
3097
3098 // Target properties.
3099 Builder.defineMacro("__REGISTER_PREFIX__", "");
3100
3101 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3102 // functions in glibc header files that use FP Stack inline asm which the
3103 // backend can't deal with (PR879).
3104 Builder.defineMacro("__NO_MATH_INLINES");
3105
3106 if (HasAES)
3107 Builder.defineMacro("__AES__");
3108
3109 if (HasPCLMUL)
3110 Builder.defineMacro("__PCLMUL__");
3111
3112 if (HasLZCNT)
3113 Builder.defineMacro("__LZCNT__");
3114
3115 if (HasRDRND)
3116 Builder.defineMacro("__RDRND__");
3117
3118 if (HasFSGSBASE)
3119 Builder.defineMacro("__FSGSBASE__");
3120
3121 if (HasBMI)
3122 Builder.defineMacro("__BMI__");
3123
3124 if (HasBMI2)
3125 Builder.defineMacro("__BMI2__");
3126
3127 if (HasPOPCNT)
3128 Builder.defineMacro("__POPCNT__");
3129
3130 if (HasRTM)
3131 Builder.defineMacro("__RTM__");
3132
3133 if (HasPRFCHW)
3134 Builder.defineMacro("__PRFCHW__");
3135
3136 if (HasRDSEED)
3137 Builder.defineMacro("__RDSEED__");
3138
3139 if (HasADX)
3140 Builder.defineMacro("__ADX__");
3141
3142 if (HasTBM)
3143 Builder.defineMacro("__TBM__");
3144
3145 switch (XOPLevel) {
3146 case XOP:
3147 Builder.defineMacro("__XOP__");
3148 case FMA4:
3149 Builder.defineMacro("__FMA4__");
3150 case SSE4A:
3151 Builder.defineMacro("__SSE4A__");
3152 case NoXOP:
3153 break;
3154 }
3155
3156 if (HasFMA)
3157 Builder.defineMacro("__FMA__");
3158
3159 if (HasF16C)
3160 Builder.defineMacro("__F16C__");
3161
3162 if (HasAVX512CD)
3163 Builder.defineMacro("__AVX512CD__");
3164 if (HasAVX512ER)
3165 Builder.defineMacro("__AVX512ER__");
3166 if (HasAVX512PF)
3167 Builder.defineMacro("__AVX512PF__");
3168 if (HasAVX512DQ)
3169 Builder.defineMacro("__AVX512DQ__");
3170 if (HasAVX512BW)
3171 Builder.defineMacro("__AVX512BW__");
3172 if (HasAVX512VL)
3173 Builder.defineMacro("__AVX512VL__");
3174
3175 if (HasSHA)
3176 Builder.defineMacro("__SHA__");
3177
3178 if (HasCX16)
3179 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3180
3181 // Each case falls through to the previous one here.
3182 switch (SSELevel) {
3183 case AVX512F:
3184 Builder.defineMacro("__AVX512F__");
3185 case AVX2:
3186 Builder.defineMacro("__AVX2__");
3187 case AVX:
3188 Builder.defineMacro("__AVX__");
3189 case SSE42:
3190 Builder.defineMacro("__SSE4_2__");
3191 case SSE41:
3192 Builder.defineMacro("__SSE4_1__");
3193 case SSSE3:
3194 Builder.defineMacro("__SSSE3__");
3195 case SSE3:
3196 Builder.defineMacro("__SSE3__");
3197 case SSE2:
3198 Builder.defineMacro("__SSE2__");
3199 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3200 case SSE1:
3201 Builder.defineMacro("__SSE__");
3202 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3203 case NoSSE:
3204 break;
3205 }
3206
3207 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3208 switch (SSELevel) {
3209 case AVX512F:
3210 case AVX2:
3211 case AVX:
3212 case SSE42:
3213 case SSE41:
3214 case SSSE3:
3215 case SSE3:
3216 case SSE2:
3217 Builder.defineMacro("_M_IX86_FP", Twine(2));
3218 break;
3219 case SSE1:
3220 Builder.defineMacro("_M_IX86_FP", Twine(1));
3221 break;
3222 default:
3223 Builder.defineMacro("_M_IX86_FP", Twine(0));
3224 }
3225 }
3226
3227 // Each case falls through to the previous one here.
3228 switch (MMX3DNowLevel) {
3229 case AMD3DNowAthlon:
3230 Builder.defineMacro("__3dNOW_A__");
3231 case AMD3DNow:
3232 Builder.defineMacro("__3dNOW__");
3233 case MMX:
3234 Builder.defineMacro("__MMX__");
3235 case NoMMX3DNow:
3236 break;
3237 }
3238
3239 if (CPU >= CK_i486) {
3240 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3241 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3242 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3243 }
3244 if (CPU >= CK_i586)
3245 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3246 }
3247
hasFeature(StringRef Feature) const3248 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3249 return llvm::StringSwitch<bool>(Feature)
3250 .Case("aes", HasAES)
3251 .Case("avx", SSELevel >= AVX)
3252 .Case("avx2", SSELevel >= AVX2)
3253 .Case("avx512f", SSELevel >= AVX512F)
3254 .Case("avx512cd", HasAVX512CD)
3255 .Case("avx512er", HasAVX512ER)
3256 .Case("avx512pf", HasAVX512PF)
3257 .Case("avx512dq", HasAVX512DQ)
3258 .Case("avx512bw", HasAVX512BW)
3259 .Case("avx512vl", HasAVX512VL)
3260 .Case("bmi", HasBMI)
3261 .Case("bmi2", HasBMI2)
3262 .Case("cx16", HasCX16)
3263 .Case("f16c", HasF16C)
3264 .Case("fma", HasFMA)
3265 .Case("fma4", XOPLevel >= FMA4)
3266 .Case("fsgsbase", HasFSGSBASE)
3267 .Case("lzcnt", HasLZCNT)
3268 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3269 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3270 .Case("mmx", MMX3DNowLevel >= MMX)
3271 .Case("pclmul", HasPCLMUL)
3272 .Case("popcnt", HasPOPCNT)
3273 .Case("prfchw", HasPRFCHW)
3274 .Case("rdrnd", HasRDRND)
3275 .Case("rdseed", HasRDSEED)
3276 .Case("rtm", HasRTM)
3277 .Case("sha", HasSHA)
3278 .Case("sse", SSELevel >= SSE1)
3279 .Case("sse2", SSELevel >= SSE2)
3280 .Case("sse3", SSELevel >= SSE3)
3281 .Case("ssse3", SSELevel >= SSSE3)
3282 .Case("sse4.1", SSELevel >= SSE41)
3283 .Case("sse4.2", SSELevel >= SSE42)
3284 .Case("sse4a", XOPLevel >= SSE4A)
3285 .Case("tbm", HasTBM)
3286 .Case("x86", true)
3287 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3288 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3289 .Case("xop", XOPLevel >= XOP)
3290 .Default(false);
3291 }
3292
3293 bool
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const3294 X86TargetInfo::validateAsmConstraint(const char *&Name,
3295 TargetInfo::ConstraintInfo &Info) const {
3296 switch (*Name) {
3297 default: return false;
3298 case 'I':
3299 Info.setRequiresImmediate(0, 31);
3300 return true;
3301 case 'J':
3302 Info.setRequiresImmediate(0, 63);
3303 return true;
3304 case 'K':
3305 Info.setRequiresImmediate(-128, 127);
3306 return true;
3307 case 'L':
3308 // FIXME: properly analyze this constraint:
3309 // must be one of 0xff, 0xffff, or 0xffffffff
3310 return true;
3311 case 'M':
3312 Info.setRequiresImmediate(0, 3);
3313 return true;
3314 case 'N':
3315 Info.setRequiresImmediate(0, 255);
3316 return true;
3317 case 'O':
3318 Info.setRequiresImmediate(0, 127);
3319 return true;
3320 case 'Y': // first letter of a pair:
3321 switch (*(Name+1)) {
3322 default: return false;
3323 case '0': // First SSE register.
3324 case 't': // Any SSE register, when SSE2 is enabled.
3325 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3326 case 'm': // any MMX register, when inter-unit moves enabled.
3327 break; // falls through to setAllowsRegister.
3328 }
3329 case 'f': // any x87 floating point stack register.
3330 // Constraint 'f' cannot be used for output operands.
3331 if (Info.ConstraintStr[0] == '=')
3332 return false;
3333
3334 Info.setAllowsRegister();
3335 return true;
3336 case 'a': // eax.
3337 case 'b': // ebx.
3338 case 'c': // ecx.
3339 case 'd': // edx.
3340 case 'S': // esi.
3341 case 'D': // edi.
3342 case 'A': // edx:eax.
3343 case 't': // top of floating point stack.
3344 case 'u': // second from top of floating point stack.
3345 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3346 case 'y': // Any MMX register.
3347 case 'x': // Any SSE register.
3348 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3349 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3350 case 'l': // "Index" registers: any general register that can be used as an
3351 // index in a base+index memory access.
3352 Info.setAllowsRegister();
3353 return true;
3354 case 'C': // SSE floating point constant.
3355 case 'G': // x87 floating point constant.
3356 case 'e': // 32-bit signed integer constant for use with zero-extending
3357 // x86_64 instructions.
3358 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3359 // x86_64 instructions.
3360 return true;
3361 }
3362 }
3363
validateOutputSize(StringRef Constraint,unsigned Size) const3364 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3365 unsigned Size) const {
3366 // Strip off constraint modifiers.
3367 while (Constraint[0] == '=' ||
3368 Constraint[0] == '+' ||
3369 Constraint[0] == '&')
3370 Constraint = Constraint.substr(1);
3371
3372 return validateOperandSize(Constraint, Size);
3373 }
3374
validateInputSize(StringRef Constraint,unsigned Size) const3375 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3376 unsigned Size) const {
3377 return validateOperandSize(Constraint, Size);
3378 }
3379
validateOperandSize(StringRef Constraint,unsigned Size) const3380 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3381 unsigned Size) const {
3382 switch (Constraint[0]) {
3383 default: break;
3384 case 'y':
3385 return Size <= 64;
3386 case 'f':
3387 case 't':
3388 case 'u':
3389 return Size <= 128;
3390 case 'x':
3391 // 256-bit ymm registers can be used if target supports AVX.
3392 return Size <= (SSELevel >= AVX ? 256U : 128U);
3393 }
3394
3395 return true;
3396 }
3397
3398 std::string
convertConstraint(const char * & Constraint) const3399 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3400 switch (*Constraint) {
3401 case 'a': return std::string("{ax}");
3402 case 'b': return std::string("{bx}");
3403 case 'c': return std::string("{cx}");
3404 case 'd': return std::string("{dx}");
3405 case 'S': return std::string("{si}");
3406 case 'D': return std::string("{di}");
3407 case 'p': // address
3408 return std::string("im");
3409 case 't': // top of floating point stack.
3410 return std::string("{st}");
3411 case 'u': // second from top of floating point stack.
3412 return std::string("{st(1)}"); // second from top of floating point stack.
3413 default:
3414 return std::string(1, *Constraint);
3415 }
3416 }
3417
3418 // X86-32 generic target
3419 class X86_32TargetInfo : public X86TargetInfo {
3420 public:
X86_32TargetInfo(const llvm::Triple & Triple)3421 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3422 DoubleAlign = LongLongAlign = 32;
3423 LongDoubleWidth = 96;
3424 LongDoubleAlign = 32;
3425 SuitableAlign = 128;
3426 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3427 SizeType = UnsignedInt;
3428 PtrDiffType = SignedInt;
3429 IntPtrType = SignedInt;
3430 RegParmMax = 3;
3431
3432 // Use fpret for all types.
3433 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3434 (1 << TargetInfo::Double) |
3435 (1 << TargetInfo::LongDouble));
3436
3437 // x86-32 has atomics up to 8 bytes
3438 // FIXME: Check that we actually have cmpxchg8b before setting
3439 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3440 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3441 }
getBuiltinVaListKind() const3442 BuiltinVaListKind getBuiltinVaListKind() const override {
3443 return TargetInfo::CharPtrBuiltinVaList;
3444 }
3445
getEHDataRegisterNumber(unsigned RegNo) const3446 int getEHDataRegisterNumber(unsigned RegNo) const override {
3447 if (RegNo == 0) return 0;
3448 if (RegNo == 1) return 2;
3449 return -1;
3450 }
validateOperandSize(StringRef Constraint,unsigned Size) const3451 bool validateOperandSize(StringRef Constraint,
3452 unsigned Size) const override {
3453 switch (Constraint[0]) {
3454 default: break;
3455 case 'R':
3456 case 'q':
3457 case 'Q':
3458 case 'a':
3459 case 'b':
3460 case 'c':
3461 case 'd':
3462 case 'S':
3463 case 'D':
3464 return Size <= 32;
3465 case 'A':
3466 return Size <= 64;
3467 }
3468
3469 return X86TargetInfo::validateOperandSize(Constraint, Size);
3470 }
3471 };
3472
3473 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3474 public:
NetBSDI386TargetInfo(const llvm::Triple & Triple)3475 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3476 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3477
getFloatEvalMethod() const3478 unsigned getFloatEvalMethod() const override {
3479 unsigned Major, Minor, Micro;
3480 getTriple().getOSVersion(Major, Minor, Micro);
3481 // New NetBSD uses the default rounding mode.
3482 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3483 return X86_32TargetInfo::getFloatEvalMethod();
3484 // NetBSD before 6.99.26 defaults to "double" rounding.
3485 return 1;
3486 }
3487 };
3488
3489 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3490 public:
OpenBSDI386TargetInfo(const llvm::Triple & Triple)3491 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3492 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3493 SizeType = UnsignedLong;
3494 IntPtrType = SignedLong;
3495 PtrDiffType = SignedLong;
3496 }
3497 };
3498
3499 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3500 public:
BitrigI386TargetInfo(const llvm::Triple & Triple)3501 BitrigI386TargetInfo(const llvm::Triple &Triple)
3502 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3503 SizeType = UnsignedLong;
3504 IntPtrType = SignedLong;
3505 PtrDiffType = SignedLong;
3506 }
3507 };
3508
3509 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3510 public:
DarwinI386TargetInfo(const llvm::Triple & Triple)3511 DarwinI386TargetInfo(const llvm::Triple &Triple)
3512 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3513 LongDoubleWidth = 128;
3514 LongDoubleAlign = 128;
3515 SuitableAlign = 128;
3516 MaxVectorAlign = 256;
3517 SizeType = UnsignedLong;
3518 IntPtrType = SignedLong;
3519 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3520 HasAlignMac68kSupport = true;
3521 }
3522
3523 };
3524
3525 // x86-32 Windows target
3526 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3527 public:
WindowsX86_32TargetInfo(const llvm::Triple & Triple)3528 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3529 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3530 WCharType = UnsignedShort;
3531 DoubleAlign = LongLongAlign = 64;
3532 bool IsWinCOFF =
3533 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3534 DescriptionString = IsWinCOFF ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-S32"
3535 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-S32";
3536 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3537 void getTargetDefines(const LangOptions &Opts,
3538 MacroBuilder &Builder) const override {
3539 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3540 }
3541 };
3542
3543 // x86-32 Windows Visual Studio target
3544 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3545 public:
MicrosoftX86_32TargetInfo(const llvm::Triple & Triple)3546 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3547 : WindowsX86_32TargetInfo(Triple) {
3548 LongDoubleWidth = LongDoubleAlign = 64;
3549 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3550 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3551 void getTargetDefines(const LangOptions &Opts,
3552 MacroBuilder &Builder) const override {
3553 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3554 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3555 // The value of the following reflects processor type.
3556 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3557 // We lost the original triple, so we use the default.
3558 Builder.defineMacro("_M_IX86", "600");
3559 }
3560 };
3561 } // end anonymous namespace
3562
addMinGWDefines(const LangOptions & Opts,MacroBuilder & Builder)3563 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3564 Builder.defineMacro("__MSVCRT__");
3565 Builder.defineMacro("__MINGW32__");
3566
3567 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports
3568 // __declspec natively under -fms-extensions, but we define a no-op __declspec
3569 // macro anyway for pre-processor compatibility.
3570 if (Opts.MicrosoftExt)
3571 Builder.defineMacro("__declspec", "__declspec");
3572 else
3573 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3574
3575 if (!Opts.MicrosoftExt) {
3576 // Provide macros for all the calling convention keywords. Provide both
3577 // single and double underscore prefixed variants. These are available on
3578 // x64 as well as x86, even though they have no effect.
3579 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3580 for (const char *CC : CCs) {
3581 std::string GCCSpelling = "__attribute__((__";
3582 GCCSpelling += CC;
3583 GCCSpelling += "__))";
3584 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3585 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3586 }
3587 }
3588 }
3589
3590 namespace {
3591 // x86-32 MinGW target
3592 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3593 public:
MinGWX86_32TargetInfo(const llvm::Triple & Triple)3594 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3595 : WindowsX86_32TargetInfo(Triple) {}
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3596 void getTargetDefines(const LangOptions &Opts,
3597 MacroBuilder &Builder) const override {
3598 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3599 DefineStd(Builder, "WIN32", Opts);
3600 DefineStd(Builder, "WINNT", Opts);
3601 Builder.defineMacro("_X86_");
3602 addMinGWDefines(Opts, Builder);
3603 }
3604 };
3605
3606 // x86-32 Cygwin target
3607 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3608 public:
CygwinX86_32TargetInfo(const llvm::Triple & Triple)3609 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3610 : X86_32TargetInfo(Triple) {
3611 TLSSupported = false;
3612 WCharType = UnsignedShort;
3613 DoubleAlign = LongLongAlign = 64;
3614 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-S32";
3615 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3616 void getTargetDefines(const LangOptions &Opts,
3617 MacroBuilder &Builder) const override {
3618 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3619 Builder.defineMacro("_X86_");
3620 Builder.defineMacro("__CYGWIN__");
3621 Builder.defineMacro("__CYGWIN32__");
3622 DefineStd(Builder, "unix", Opts);
3623 if (Opts.CPlusPlus)
3624 Builder.defineMacro("_GNU_SOURCE");
3625 }
3626 };
3627
3628 // x86-32 Haiku target
3629 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3630 public:
HaikuX86_32TargetInfo(const llvm::Triple & Triple)3631 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3632 SizeType = UnsignedLong;
3633 IntPtrType = SignedLong;
3634 PtrDiffType = SignedLong;
3635 ProcessIDType = SignedLong;
3636 this->UserLabelPrefix = "";
3637 this->TLSSupported = false;
3638 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3639 void getTargetDefines(const LangOptions &Opts,
3640 MacroBuilder &Builder) const override {
3641 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3642 Builder.defineMacro("__INTEL__");
3643 Builder.defineMacro("__HAIKU__");
3644 }
3645 };
3646
3647 // RTEMS Target
3648 template<typename Target>
3649 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3650 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const3651 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3652 MacroBuilder &Builder) const override {
3653 // RTEMS defines; list based off of gcc output
3654
3655 Builder.defineMacro("__rtems__");
3656 Builder.defineMacro("__ELF__");
3657 }
3658
3659 public:
RTEMSTargetInfo(const llvm::Triple & Triple)3660 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3661 this->UserLabelPrefix = "";
3662
3663 switch (Triple.getArch()) {
3664 default:
3665 case llvm::Triple::x86:
3666 // this->MCountName = ".mcount";
3667 break;
3668 case llvm::Triple::mips:
3669 case llvm::Triple::mipsel:
3670 case llvm::Triple::ppc:
3671 case llvm::Triple::ppc64:
3672 case llvm::Triple::ppc64le:
3673 // this->MCountName = "_mcount";
3674 break;
3675 case llvm::Triple::arm:
3676 // this->MCountName = "__mcount";
3677 break;
3678 }
3679 }
3680 };
3681
3682 // x86-32 RTEMS target
3683 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3684 public:
RTEMSX86_32TargetInfo(const llvm::Triple & Triple)3685 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3686 SizeType = UnsignedLong;
3687 IntPtrType = SignedLong;
3688 PtrDiffType = SignedLong;
3689 this->UserLabelPrefix = "";
3690 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3691 void getTargetDefines(const LangOptions &Opts,
3692 MacroBuilder &Builder) const override {
3693 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3694 Builder.defineMacro("__INTEL__");
3695 Builder.defineMacro("__rtems__");
3696 }
3697 };
3698
3699 // x86-64 generic target
3700 class X86_64TargetInfo : public X86TargetInfo {
3701 public:
X86_64TargetInfo(const llvm::Triple & Triple)3702 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3703 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3704 bool IsWinCOFF =
3705 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3706 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3707 LongDoubleWidth = 128;
3708 LongDoubleAlign = 128;
3709 LargeArrayMinWidth = 128;
3710 LargeArrayAlign = 128;
3711 SuitableAlign = 128;
3712 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3713 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3714 IntPtrType = IsX32 ? SignedInt : SignedLong;
3715 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3716 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3717 RegParmMax = 6;
3718
3719 // Pointers are 32-bit in x32.
3720 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3721 : IsWinCOFF
3722 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
3723 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3724
3725 // Use fpret only for long double.
3726 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3727
3728 // Use fp2ret for _Complex long double.
3729 ComplexLongDoubleUsesFP2Ret = true;
3730
3731 // x86-64 has atomics up to 16 bytes.
3732 MaxAtomicPromoteWidth = 128;
3733 MaxAtomicInlineWidth = 128;
3734 }
getBuiltinVaListKind() const3735 BuiltinVaListKind getBuiltinVaListKind() const override {
3736 return TargetInfo::X86_64ABIBuiltinVaList;
3737 }
3738
getEHDataRegisterNumber(unsigned RegNo) const3739 int getEHDataRegisterNumber(unsigned RegNo) const override {
3740 if (RegNo == 0) return 0;
3741 if (RegNo == 1) return 1;
3742 return -1;
3743 }
3744
checkCallingConvention(CallingConv CC) const3745 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3746 return (CC == CC_C ||
3747 CC == CC_X86VectorCall ||
3748 CC == CC_IntelOclBicc ||
3749 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3750 }
3751
getDefaultCallingConv(CallingConvMethodType MT) const3752 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3753 return CC_C;
3754 }
3755
3756 // for x32 we need it here explicitly
hasInt128Type() const3757 bool hasInt128Type() const override { return true; }
3758 };
3759
3760 // x86-64 Windows target
3761 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3762 public:
WindowsX86_64TargetInfo(const llvm::Triple & Triple)3763 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3764 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3765 WCharType = UnsignedShort;
3766 LongWidth = LongAlign = 32;
3767 DoubleAlign = LongLongAlign = 64;
3768 IntMaxType = SignedLongLong;
3769 Int64Type = SignedLongLong;
3770 SizeType = UnsignedLongLong;
3771 PtrDiffType = SignedLongLong;
3772 IntPtrType = SignedLongLong;
3773 this->UserLabelPrefix = "";
3774 }
3775
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3776 void getTargetDefines(const LangOptions &Opts,
3777 MacroBuilder &Builder) const override {
3778 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3779 Builder.defineMacro("_WIN64");
3780 }
3781
getBuiltinVaListKind() const3782 BuiltinVaListKind getBuiltinVaListKind() const override {
3783 return TargetInfo::CharPtrBuiltinVaList;
3784 }
3785
checkCallingConvention(CallingConv CC) const3786 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3787 switch (CC) {
3788 case CC_X86StdCall:
3789 case CC_X86ThisCall:
3790 case CC_X86FastCall:
3791 return CCCR_Ignore;
3792 case CC_C:
3793 case CC_X86VectorCall:
3794 case CC_IntelOclBicc:
3795 case CC_X86_64SysV:
3796 return CCCR_OK;
3797 default:
3798 return CCCR_Warning;
3799 }
3800 }
3801 };
3802
3803 // x86-64 Windows Visual Studio target
3804 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3805 public:
MicrosoftX86_64TargetInfo(const llvm::Triple & Triple)3806 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3807 : WindowsX86_64TargetInfo(Triple) {
3808 LongDoubleWidth = LongDoubleAlign = 64;
3809 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3810 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3811 void getTargetDefines(const LangOptions &Opts,
3812 MacroBuilder &Builder) const override {
3813 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3814 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3815 Builder.defineMacro("_M_X64");
3816 Builder.defineMacro("_M_AMD64");
3817 }
3818 };
3819
3820 // x86-64 MinGW target
3821 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3822 public:
MinGWX86_64TargetInfo(const llvm::Triple & Triple)3823 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3824 : WindowsX86_64TargetInfo(Triple) {}
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const3825 void getTargetDefines(const LangOptions &Opts,
3826 MacroBuilder &Builder) const override {
3827 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3828 DefineStd(Builder, "WIN64", Opts);
3829 Builder.defineMacro("__MINGW64__");
3830 addMinGWDefines(Opts, Builder);
3831
3832 // GCC defines this macro when it is using __gxx_personality_seh0.
3833 if (!Opts.SjLjExceptions)
3834 Builder.defineMacro("__SEH__");
3835 }
3836 };
3837
3838 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3839 public:
DarwinX86_64TargetInfo(const llvm::Triple & Triple)3840 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3841 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3842 Int64Type = SignedLongLong;
3843 MaxVectorAlign = 256;
3844 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3845 llvm::Triple T = llvm::Triple(Triple);
3846 if (T.isiOS())
3847 UseSignedCharForObjCBool = false;
3848 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3849 }
3850 };
3851
3852 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3853 public:
OpenBSDX86_64TargetInfo(const llvm::Triple & Triple)3854 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3855 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3856 IntMaxType = SignedLongLong;
3857 Int64Type = SignedLongLong;
3858 }
3859 };
3860
3861 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3862 public:
BitrigX86_64TargetInfo(const llvm::Triple & Triple)3863 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3864 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3865 IntMaxType = SignedLongLong;
3866 Int64Type = SignedLongLong;
3867 }
3868 };
3869
3870 class ARMTargetInfo : public TargetInfo {
3871 // Possible FPU choices.
3872 enum FPUMode {
3873 VFP2FPU = (1 << 0),
3874 VFP3FPU = (1 << 1),
3875 VFP4FPU = (1 << 2),
3876 NeonFPU = (1 << 3),
3877 FPARMV8 = (1 << 4)
3878 };
3879
3880 // Possible HWDiv features.
3881 enum HWDivMode {
3882 HWDivThumb = (1 << 0),
3883 HWDivARM = (1 << 1)
3884 };
3885
FPUModeIsVFP(FPUMode Mode)3886 static bool FPUModeIsVFP(FPUMode Mode) {
3887 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3888 }
3889
3890 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3891 static const char * const GCCRegNames[];
3892
3893 std::string ABI, CPU;
3894
3895 enum {
3896 FP_Default,
3897 FP_VFP,
3898 FP_Neon
3899 } FPMath;
3900
3901 unsigned FPU : 5;
3902
3903 unsigned IsAAPCS : 1;
3904 unsigned IsThumb : 1;
3905 unsigned HWDiv : 2;
3906
3907 // Initialized via features.
3908 unsigned SoftFloat : 1;
3909 unsigned SoftFloatABI : 1;
3910
3911 unsigned CRC : 1;
3912 unsigned Crypto : 1;
3913
3914 // ACLE 6.5.1 Hardware floating point
3915 enum {
3916 HW_FP_HP = (1 << 1), /// half (16-bit)
3917 HW_FP_SP = (1 << 2), /// single (32-bit)
3918 HW_FP_DP = (1 << 3), /// double (64-bit)
3919 };
3920 uint32_t HW_FP;
3921
3922 static const Builtin::Info BuiltinInfo[];
3923
shouldUseInlineAtomic(const llvm::Triple & T)3924 static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3925 StringRef ArchName = T.getArchName();
3926 if (T.getArch() == llvm::Triple::arm ||
3927 T.getArch() == llvm::Triple::armeb) {
3928 StringRef VersionStr;
3929 if (ArchName.startswith("armv"))
3930 VersionStr = ArchName.substr(4, 1);
3931 else if (ArchName.startswith("armebv"))
3932 VersionStr = ArchName.substr(6, 1);
3933 else
3934 return false;
3935 unsigned Version;
3936 if (VersionStr.getAsInteger(10, Version))
3937 return false;
3938 return Version >= 6;
3939 }
3940 assert(T.getArch() == llvm::Triple::thumb ||
3941 T.getArch() == llvm::Triple::thumbeb);
3942 StringRef VersionStr;
3943 if (ArchName.startswith("thumbv"))
3944 VersionStr = ArchName.substr(6, 1);
3945 else if (ArchName.startswith("thumbebv"))
3946 VersionStr = ArchName.substr(8, 1);
3947 else
3948 return false;
3949 unsigned Version;
3950 if (VersionStr.getAsInteger(10, Version))
3951 return false;
3952 return Version >= 7;
3953 }
3954
setABIAAPCS()3955 void setABIAAPCS() {
3956 IsAAPCS = true;
3957
3958 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3959 const llvm::Triple &T = getTriple();
3960
3961 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
3962 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
3963 T.getOS() == llvm::Triple::Bitrig)
3964 SizeType = UnsignedLong;
3965 else
3966 SizeType = UnsignedInt;
3967
3968 switch (T.getOS()) {
3969 case llvm::Triple::NetBSD:
3970 WCharType = SignedInt;
3971 break;
3972 case llvm::Triple::Win32:
3973 WCharType = UnsignedShort;
3974 break;
3975 case llvm::Triple::Linux:
3976 default:
3977 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3978 WCharType = UnsignedInt;
3979 break;
3980 }
3981
3982 UseBitFieldTypeAlignment = true;
3983
3984 ZeroLengthBitfieldBoundary = 0;
3985
3986 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3987 // so set preferred for small types to 32.
3988 if (T.isOSBinFormatMachO()) {
3989 DescriptionString =
3990 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3991 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3992 } else if (T.isOSWindows()) {
3993 assert(!BigEndian && "Windows on ARM does not support big endian");
3994 DescriptionString = "e"
3995 "-m:w"
3996 "-p:32:32"
3997 "-i64:64"
3998 "-v128:64:128"
3999 "-a:0:32"
4000 "-n32"
4001 "-S64";
4002 } else if (T.isOSNaCl()) {
4003 assert(!BigEndian && "NaCl on ARM does not support big endian");
4004 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
4005 } else {
4006 DescriptionString =
4007 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4008 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4009 }
4010
4011 // FIXME: Enumerated types are variable width in straight AAPCS.
4012 }
4013
setABIAPCS()4014 void setABIAPCS() {
4015 const llvm::Triple &T = getTriple();
4016
4017 IsAAPCS = false;
4018
4019 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4020
4021 // size_t is unsigned int on FreeBSD.
4022 if (T.getOS() == llvm::Triple::FreeBSD)
4023 SizeType = UnsignedInt;
4024 else
4025 SizeType = UnsignedLong;
4026
4027 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4028 WCharType = SignedInt;
4029
4030 // Do not respect the alignment of bit-field types when laying out
4031 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4032 UseBitFieldTypeAlignment = false;
4033
4034 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4035 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4036 /// gcc.
4037 ZeroLengthBitfieldBoundary = 32;
4038
4039 if (T.isOSBinFormatMachO())
4040 DescriptionString =
4041 BigEndian
4042 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4043 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4044 else
4045 DescriptionString =
4046 BigEndian
4047 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4048 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4049
4050 // FIXME: Override "preferred align" for double and long long.
4051 }
4052
4053 public:
ARMTargetInfo(const llvm::Triple & Triple,bool IsBigEndian)4054 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
4055 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
4056 IsAAPCS(true), HW_FP(0) {
4057 BigEndian = IsBigEndian;
4058
4059 switch (getTriple().getOS()) {
4060 case llvm::Triple::NetBSD:
4061 PtrDiffType = SignedLong;
4062 break;
4063 default:
4064 PtrDiffType = SignedInt;
4065 break;
4066 }
4067
4068 // {} in inline assembly are neon specifiers, not assembly variant
4069 // specifiers.
4070 NoAsmVariants = true;
4071
4072 // FIXME: Should we just treat this as a feature?
4073 IsThumb = getTriple().getArchName().startswith("thumb");
4074
4075 // FIXME: This duplicates code from the driver that sets the -target-abi
4076 // option - this code is used if -target-abi isn't passed and should
4077 // be unified in some way.
4078 if (Triple.isOSBinFormatMachO()) {
4079 // The backend is hardwired to assume AAPCS for M-class processors, ensure
4080 // the frontend matches that.
4081 if (Triple.getEnvironment() == llvm::Triple::EABI ||
4082 Triple.getOS() == llvm::Triple::UnknownOS ||
4083 StringRef(CPU).startswith("cortex-m")) {
4084 setABI("aapcs");
4085 } else {
4086 setABI("apcs-gnu");
4087 }
4088 } else if (Triple.isOSWindows()) {
4089 // FIXME: this is invalid for WindowsCE
4090 setABI("aapcs");
4091 } else {
4092 // Select the default based on the platform.
4093 switch (Triple.getEnvironment()) {
4094 case llvm::Triple::Android:
4095 case llvm::Triple::GNUEABI:
4096 case llvm::Triple::GNUEABIHF:
4097 setABI("aapcs-linux");
4098 break;
4099 case llvm::Triple::EABIHF:
4100 case llvm::Triple::EABI:
4101 setABI("aapcs");
4102 break;
4103 case llvm::Triple::GNU:
4104 setABI("apcs-gnu");
4105 break;
4106 default:
4107 if (Triple.getOS() == llvm::Triple::NetBSD)
4108 setABI("apcs-gnu");
4109 else
4110 setABI("aapcs");
4111 break;
4112 }
4113 }
4114
4115 // ARM targets default to using the ARM C++ ABI.
4116 TheCXXABI.set(TargetCXXABI::GenericARM);
4117
4118 // ARM has atomics up to 8 bytes
4119 MaxAtomicPromoteWidth = 64;
4120 if (shouldUseInlineAtomic(getTriple()))
4121 MaxAtomicInlineWidth = 64;
4122
4123 // Do force alignment of members that follow zero length bitfields. If
4124 // the alignment of the zero-length bitfield is greater than the member
4125 // that follows it, `bar', `bar' will be aligned as the type of the
4126 // zero length bitfield.
4127 UseZeroLengthBitfieldAlignment = true;
4128 }
getABI() const4129 StringRef getABI() const override { return ABI; }
setABI(const std::string & Name)4130 bool setABI(const std::string &Name) override {
4131 ABI = Name;
4132
4133 // The defaults (above) are for AAPCS, check if we need to change them.
4134 //
4135 // FIXME: We need support for -meabi... we could just mangle it into the
4136 // name.
4137 if (Name == "apcs-gnu") {
4138 setABIAPCS();
4139 return true;
4140 }
4141 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4142 setABIAAPCS();
4143 return true;
4144 }
4145 return false;
4146 }
4147
getDefaultFeatures(llvm::StringMap<bool> & Features) const4148 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
4149 StringRef ArchName = getTriple().getArchName();
4150 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
4151 Features["vfp2"] = true;
4152 else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
4153 Features["vfp3"] = true;
4154 Features["neon"] = true;
4155 }
4156 else if (CPU == "cortex-a5") {
4157 Features["vfp4"] = true;
4158 Features["neon"] = true;
4159 } else if (CPU == "swift" || CPU == "cortex-a7" ||
4160 CPU == "cortex-a12" || CPU == "cortex-a15" ||
4161 CPU == "cortex-a17" || CPU == "krait") {
4162 Features["vfp4"] = true;
4163 Features["neon"] = true;
4164 Features["hwdiv"] = true;
4165 Features["hwdiv-arm"] = true;
4166 } else if (CPU == "cyclone") {
4167 Features["v8fp"] = true;
4168 Features["neon"] = true;
4169 Features["hwdiv"] = true;
4170 Features["hwdiv-arm"] = true;
4171 } else if (CPU == "cortex-a53" || CPU == "cortex-a57" || CPU == "cortex-a72") {
4172 Features["fp-armv8"] = true;
4173 Features["neon"] = true;
4174 Features["hwdiv"] = true;
4175 Features["hwdiv-arm"] = true;
4176 Features["crc"] = true;
4177 Features["crypto"] = true;
4178 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" ||
4179 // Enable the hwdiv extension for all v8a AArch32 cores by
4180 // default.
4181 ArchName == "armv8a" || ArchName == "armv8" ||
4182 ArchName == "armebv8a" || ArchName == "armebv8" ||
4183 ArchName == "thumbv8a" || ArchName == "thumbv8" ||
4184 ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
4185 Features["hwdiv"] = true;
4186 Features["hwdiv-arm"] = true;
4187 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
4188 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") {
4189 Features["hwdiv"] = true;
4190 }
4191 }
4192
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)4193 bool handleTargetFeatures(std::vector<std::string> &Features,
4194 DiagnosticsEngine &Diags) override {
4195 FPU = 0;
4196 CRC = 0;
4197 Crypto = 0;
4198 SoftFloat = SoftFloatABI = false;
4199 HWDiv = 0;
4200
4201 for (const auto &Feature : Features) {
4202 if (Feature == "+soft-float") {
4203 SoftFloat = true;
4204 } else if (Feature == "+soft-float-abi") {
4205 SoftFloatABI = true;
4206 } else if (Feature == "+vfp2") {
4207 FPU |= VFP2FPU;
4208 HW_FP = HW_FP_SP | HW_FP_DP;
4209 } else if (Feature == "+vfp3") {
4210 FPU |= VFP3FPU;
4211 HW_FP = HW_FP_SP | HW_FP_DP;
4212 } else if (Feature == "+vfp4") {
4213 FPU |= VFP4FPU;
4214 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4215 } else if (Feature == "+fp-armv8") {
4216 FPU |= FPARMV8;
4217 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4218 } else if (Feature == "+neon") {
4219 FPU |= NeonFPU;
4220 HW_FP = HW_FP_SP | HW_FP_DP;
4221 } else if (Feature == "+long64") {
4222 LongWidth = LongAlign = 64; // RenderScript uses a 64-bit long type
4223 } else if (Feature == "+hwdiv") {
4224 HWDiv |= HWDivThumb;
4225 } else if (Feature == "+hwdiv-arm") {
4226 HWDiv |= HWDivARM;
4227 } else if (Feature == "+crc") {
4228 CRC = 1;
4229 } else if (Feature == "+crypto") {
4230 Crypto = 1;
4231 } else if (Feature == "+fp-only-sp") {
4232 HW_FP &= ~HW_FP_DP;
4233 }
4234 }
4235
4236 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4237 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4238 return false;
4239 }
4240
4241 if (FPMath == FP_Neon)
4242 Features.push_back("+neonfp");
4243 else if (FPMath == FP_VFP)
4244 Features.push_back("-neonfp");
4245
4246 // Remove front-end specific options which the backend handles differently.
4247 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
4248 for (const auto &FEFeature : FrontEndFeatures) {
4249 auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
4250 if (Feature != Features.end())
4251 Features.erase(Feature);
4252 }
4253
4254 return true;
4255 }
4256
hasFeature(StringRef Feature) const4257 bool hasFeature(StringRef Feature) const override {
4258 return llvm::StringSwitch<bool>(Feature)
4259 .Case("arm", true)
4260 .Case("softfloat", SoftFloat)
4261 .Case("thumb", IsThumb)
4262 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4263 .Case("hwdiv", HWDiv & HWDivThumb)
4264 .Case("hwdiv-arm", HWDiv & HWDivARM)
4265 .Default(false);
4266 }
4267 // FIXME: Should we actually have some table instead of these switches?
getCPUDefineSuffix(StringRef Name)4268 static const char *getCPUDefineSuffix(StringRef Name) {
4269 return llvm::StringSwitch<const char *>(Name)
4270 .Cases("arm8", "arm810", "4")
4271 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
4272 "4")
4273 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4274 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4275 .Case("ep9312", "4T")
4276 .Cases("arm10tdmi", "arm1020t", "5T")
4277 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4278 .Case("arm926ej-s", "5TEJ")
4279 .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4280 .Cases("xscale", "iwmmxt", "5TE")
4281 .Case("arm1136j-s", "6J")
4282 .Case("arm1136jf-s", "6")
4283 .Cases("mpcorenovfp", "mpcore", "6K")
4284 .Cases("arm1176jz-s", "arm1176jzf-s", "6K")
4285 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4286 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
4287 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4288 "7A")
4289 .Cases("cortex-r4", "cortex-r4f", "cortex-r5", "cortex-r7", "7R")
4290 .Case("swift", "7S")
4291 .Case("cyclone", "8A")
4292 .Cases("sc300", "cortex-m3", "7M")
4293 .Cases("cortex-m4", "cortex-m7", "7EM")
4294 .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M")
4295 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A")
4296 .Default(nullptr);
4297 }
getCPUProfile(StringRef Name)4298 static const char *getCPUProfile(StringRef Name) {
4299 return llvm::StringSwitch<const char *>(Name)
4300 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4301 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4302 "A")
4303 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "A")
4304 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m0plus", "M")
4305 .Cases("cortex-m1", "cortex-m7", "sc000", "sc300", "M")
4306 .Cases("cortex-r4", "cortex-r4f", "cortex-r5", "cortex-r7", "R")
4307 .Default("");
4308 }
setCPU(const std::string & Name)4309 bool setCPU(const std::string &Name) override {
4310 if (!getCPUDefineSuffix(Name))
4311 return false;
4312
4313 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4314 StringRef Profile = getCPUProfile(Name);
4315 if (Profile == "M" && MaxAtomicInlineWidth) {
4316 MaxAtomicPromoteWidth = 32;
4317 MaxAtomicInlineWidth = 32;
4318 }
4319
4320 CPU = Name;
4321 return true;
4322 }
4323 bool setFPMath(StringRef Name) override;
supportsThumb(StringRef ArchName,StringRef CPUArch,unsigned CPUArchVer) const4324 bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4325 unsigned CPUArchVer) const {
4326 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4327 (CPUArch.find('M') != StringRef::npos);
4328 }
supportsThumb2(StringRef ArchName,StringRef CPUArch,unsigned CPUArchVer) const4329 bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4330 unsigned CPUArchVer) const {
4331 // We check both CPUArchVer and ArchName because when only triple is
4332 // specified, the default CPU is arm1136j-s.
4333 return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4334 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4335 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4336 void getTargetDefines(const LangOptions &Opts,
4337 MacroBuilder &Builder) const override {
4338 // Target identification.
4339 Builder.defineMacro("__arm");
4340 Builder.defineMacro("__arm__");
4341
4342 // Target properties.
4343 Builder.defineMacro("__REGISTER_PREFIX__", "");
4344
4345 StringRef CPUArch = getCPUDefineSuffix(CPU);
4346 unsigned int CPUArchVer;
4347 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4348 llvm_unreachable("Invalid char for architecture version number");
4349 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4350
4351 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4352 StringRef CPUProfile = getCPUProfile(CPU);
4353 StringRef ArchName = getTriple().getArchName();
4354
4355 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4356 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4357 if (CPUArch[0] >= '8') {
4358 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4359 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4360 }
4361
4362 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4363 // is not defined for the M-profile.
4364 // NOTE that the deffault profile is assumed to be 'A'
4365 if (CPUProfile.empty() || CPUProfile != "M")
4366 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4367
4368 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4369 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4370 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4371 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4372 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4373 else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4374 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4375
4376 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4377 // instruction set such as ARM or Thumb.
4378 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4379
4380 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4381
4382 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4383 if (!CPUProfile.empty())
4384 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4385
4386 // ACLE 6.5.1 Hardware Floating Point
4387 if (HW_FP)
4388 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4389
4390 // ACLE predefines.
4391 Builder.defineMacro("__ARM_ACLE", "200");
4392
4393 // Subtarget options.
4394
4395 // FIXME: It's more complicated than this and we don't really support
4396 // interworking.
4397 // Windows on ARM does not "support" interworking
4398 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4399 Builder.defineMacro("__THUMB_INTERWORK__");
4400
4401 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4402 // Embedded targets on Darwin follow AAPCS, but not EABI.
4403 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4404 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4405 Builder.defineMacro("__ARM_EABI__");
4406 Builder.defineMacro("__ARM_PCS", "1");
4407
4408 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4409 Builder.defineMacro("__ARM_PCS_VFP", "1");
4410 }
4411
4412 if (SoftFloat)
4413 Builder.defineMacro("__SOFTFP__");
4414
4415 if (CPU == "xscale")
4416 Builder.defineMacro("__XSCALE__");
4417
4418 if (IsThumb) {
4419 Builder.defineMacro("__THUMBEL__");
4420 Builder.defineMacro("__thumb__");
4421 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4422 Builder.defineMacro("__thumb2__");
4423 }
4424 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4425 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4426
4427 // Note, this is always on in gcc, even though it doesn't make sense.
4428 Builder.defineMacro("__APCS_32__");
4429
4430 if (FPUModeIsVFP((FPUMode) FPU)) {
4431 Builder.defineMacro("__VFP_FP__");
4432 if (FPU & VFP2FPU)
4433 Builder.defineMacro("__ARM_VFPV2__");
4434 if (FPU & VFP3FPU)
4435 Builder.defineMacro("__ARM_VFPV3__");
4436 if (FPU & VFP4FPU)
4437 Builder.defineMacro("__ARM_VFPV4__");
4438 }
4439
4440 // This only gets set when Neon instructions are actually available, unlike
4441 // the VFP define, hence the soft float and arch check. This is subtly
4442 // different from gcc, we follow the intent which was that it should be set
4443 // when Neon instructions are actually available.
4444 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4445 Builder.defineMacro("__ARM_NEON");
4446 Builder.defineMacro("__ARM_NEON__");
4447 }
4448
4449 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4450 Opts.ShortWChar ? "2" : "4");
4451
4452 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4453 Opts.ShortEnums ? "1" : "4");
4454
4455 if (CRC)
4456 Builder.defineMacro("__ARM_FEATURE_CRC32");
4457
4458 if (Crypto)
4459 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4460
4461 if (CPUArchVer >= 6 && CPUArch != "6M") {
4462 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4463 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4464 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4465 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4466 }
4467
4468 bool is5EOrAbove = (CPUArchVer >= 6 ||
4469 (CPUArchVer == 5 &&
4470 CPUArch.find('E') != StringRef::npos));
4471 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4472 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM"))
4473 Builder.defineMacro("__ARM_FEATURE_DSP");
4474 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const4475 void getTargetBuiltins(const Builtin::Info *&Records,
4476 unsigned &NumRecords) const override {
4477 Records = BuiltinInfo;
4478 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4479 }
isCLZForZeroUndef() const4480 bool isCLZForZeroUndef() const override { return false; }
getBuiltinVaListKind() const4481 BuiltinVaListKind getBuiltinVaListKind() const override {
4482 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4483 }
4484 void getGCCRegNames(const char * const *&Names,
4485 unsigned &NumNames) const override;
4486 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4487 unsigned &NumAliases) const override;
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const4488 bool validateAsmConstraint(const char *&Name,
4489 TargetInfo::ConstraintInfo &Info) const override {
4490 switch (*Name) {
4491 default: break;
4492 case 'l': // r0-r7
4493 case 'h': // r8-r15
4494 case 'w': // VFP Floating point register single precision
4495 case 'P': // VFP Floating point register double precision
4496 Info.setAllowsRegister();
4497 return true;
4498 case 'I':
4499 case 'J':
4500 case 'K':
4501 case 'L':
4502 case 'M':
4503 // FIXME
4504 return true;
4505 case 'Q': // A memory address that is a single base register.
4506 Info.setAllowsMemory();
4507 return true;
4508 case 'U': // a memory reference...
4509 switch (Name[1]) {
4510 case 'q': // ...ARMV4 ldrsb
4511 case 'v': // ...VFP load/store (reg+constant offset)
4512 case 'y': // ...iWMMXt load/store
4513 case 't': // address valid for load/store opaque types wider
4514 // than 128-bits
4515 case 'n': // valid address for Neon doubleword vector load/store
4516 case 'm': // valid address for Neon element and structure load/store
4517 case 's': // valid address for non-offset loads/stores of quad-word
4518 // values in four ARM registers
4519 Info.setAllowsMemory();
4520 Name++;
4521 return true;
4522 }
4523 }
4524 return false;
4525 }
convertConstraint(const char * & Constraint) const4526 std::string convertConstraint(const char *&Constraint) const override {
4527 std::string R;
4528 switch (*Constraint) {
4529 case 'U': // Two-character constraint; add "^" hint for later parsing.
4530 R = std::string("^") + std::string(Constraint, 2);
4531 Constraint++;
4532 break;
4533 case 'p': // 'p' should be translated to 'r' by default.
4534 R = std::string("r");
4535 break;
4536 default:
4537 return std::string(1, *Constraint);
4538 }
4539 return R;
4540 }
4541 bool
validateConstraintModifier(StringRef Constraint,char Modifier,unsigned Size,std::string & SuggestedModifier) const4542 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4543 std::string &SuggestedModifier) const override {
4544 bool isOutput = (Constraint[0] == '=');
4545 bool isInOut = (Constraint[0] == '+');
4546
4547 // Strip off constraint modifiers.
4548 while (Constraint[0] == '=' ||
4549 Constraint[0] == '+' ||
4550 Constraint[0] == '&')
4551 Constraint = Constraint.substr(1);
4552
4553 switch (Constraint[0]) {
4554 default: break;
4555 case 'r': {
4556 switch (Modifier) {
4557 default:
4558 return (isInOut || isOutput || Size <= 64);
4559 case 'q':
4560 // A register of size 32 cannot fit a vector type.
4561 return false;
4562 }
4563 }
4564 }
4565
4566 return true;
4567 }
getClobbers() const4568 const char *getClobbers() const override {
4569 // FIXME: Is this really right?
4570 return "";
4571 }
4572
checkCallingConvention(CallingConv CC) const4573 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4574 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4575 }
4576
getEHDataRegisterNumber(unsigned RegNo) const4577 int getEHDataRegisterNumber(unsigned RegNo) const override {
4578 if (RegNo == 0) return 0;
4579 if (RegNo == 1) return 1;
4580 return -1;
4581 }
4582 };
4583
setFPMath(StringRef Name)4584 bool ARMTargetInfo::setFPMath(StringRef Name) {
4585 if (Name == "neon") {
4586 FPMath = FP_Neon;
4587 return true;
4588 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4589 Name == "vfp4") {
4590 FPMath = FP_VFP;
4591 return true;
4592 }
4593 return false;
4594 }
4595
4596 const char * const ARMTargetInfo::GCCRegNames[] = {
4597 // Integer registers
4598 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4599 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4600
4601 // Float registers
4602 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4603 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4604 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4605 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4606
4607 // Double registers
4608 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4609 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4610 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4611 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4612
4613 // Quad registers
4614 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4615 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4616 };
4617
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const4618 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4619 unsigned &NumNames) const {
4620 Names = GCCRegNames;
4621 NumNames = llvm::array_lengthof(GCCRegNames);
4622 }
4623
4624 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4625 { { "a1" }, "r0" },
4626 { { "a2" }, "r1" },
4627 { { "a3" }, "r2" },
4628 { { "a4" }, "r3" },
4629 { { "v1" }, "r4" },
4630 { { "v2" }, "r5" },
4631 { { "v3" }, "r6" },
4632 { { "v4" }, "r7" },
4633 { { "v5" }, "r8" },
4634 { { "v6", "rfp" }, "r9" },
4635 { { "sl" }, "r10" },
4636 { { "fp" }, "r11" },
4637 { { "ip" }, "r12" },
4638 { { "r13" }, "sp" },
4639 { { "r14" }, "lr" },
4640 { { "r15" }, "pc" },
4641 // The S, D and Q registers overlap, but aren't really aliases; we
4642 // don't want to substitute one of these for a different-sized one.
4643 };
4644
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const4645 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4646 unsigned &NumAliases) const {
4647 Aliases = GCCRegAliases;
4648 NumAliases = llvm::array_lengthof(GCCRegAliases);
4649 }
4650
4651 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4652 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4653 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4654 ALL_LANGUAGES },
4655 #include "clang/Basic/BuiltinsNEON.def"
4656
4657 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4658 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4659 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4660 ALL_LANGUAGES },
4661 #include "clang/Basic/BuiltinsARM.def"
4662 };
4663
4664 class ARMleTargetInfo : public ARMTargetInfo {
4665 public:
ARMleTargetInfo(const llvm::Triple & Triple)4666 ARMleTargetInfo(const llvm::Triple &Triple)
4667 : ARMTargetInfo(Triple, false) { }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4668 void getTargetDefines(const LangOptions &Opts,
4669 MacroBuilder &Builder) const override {
4670 Builder.defineMacro("__ARMEL__");
4671 ARMTargetInfo::getTargetDefines(Opts, Builder);
4672 }
4673 };
4674
4675 class ARMbeTargetInfo : public ARMTargetInfo {
4676 public:
ARMbeTargetInfo(const llvm::Triple & Triple)4677 ARMbeTargetInfo(const llvm::Triple &Triple)
4678 : ARMTargetInfo(Triple, true) { }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4679 void getTargetDefines(const LangOptions &Opts,
4680 MacroBuilder &Builder) const override {
4681 Builder.defineMacro("__ARMEB__");
4682 Builder.defineMacro("__ARM_BIG_ENDIAN");
4683 ARMTargetInfo::getTargetDefines(Opts, Builder);
4684 }
4685 };
4686
4687 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4688 const llvm::Triple Triple;
4689 public:
WindowsARMTargetInfo(const llvm::Triple & Triple)4690 WindowsARMTargetInfo(const llvm::Triple &Triple)
4691 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4692 TLSSupported = false;
4693 WCharType = UnsignedShort;
4694 SizeType = UnsignedInt;
4695 UserLabelPrefix = "";
4696 }
getVisualStudioDefines(const LangOptions & Opts,MacroBuilder & Builder) const4697 void getVisualStudioDefines(const LangOptions &Opts,
4698 MacroBuilder &Builder) const {
4699 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4700
4701 // FIXME: this is invalid for WindowsCE
4702 Builder.defineMacro("_M_ARM_NT", "1");
4703 Builder.defineMacro("_M_ARMT", "_M_ARM");
4704 Builder.defineMacro("_M_THUMB", "_M_ARM");
4705
4706 assert((Triple.getArch() == llvm::Triple::arm ||
4707 Triple.getArch() == llvm::Triple::thumb) &&
4708 "invalid architecture for Windows ARM target info");
4709 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4710 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4711
4712 // TODO map the complete set of values
4713 // 31: VFPv3 40: VFPv4
4714 Builder.defineMacro("_M_ARM_FP", "31");
4715 }
getBuiltinVaListKind() const4716 BuiltinVaListKind getBuiltinVaListKind() const override {
4717 return TargetInfo::CharPtrBuiltinVaList;
4718 }
4719 };
4720
4721 // Windows ARM + Itanium C++ ABI Target
4722 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4723 public:
ItaniumWindowsARMleTargetInfo(const llvm::Triple & Triple)4724 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4725 : WindowsARMTargetInfo(Triple) {
4726 TheCXXABI.set(TargetCXXABI::GenericARM);
4727 }
4728
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4729 void getTargetDefines(const LangOptions &Opts,
4730 MacroBuilder &Builder) const override {
4731 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4732
4733 if (Opts.MSVCCompat)
4734 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4735 }
4736 };
4737
4738 // Windows ARM, MS (C++) ABI
4739 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4740 public:
MicrosoftARMleTargetInfo(const llvm::Triple & Triple)4741 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4742 : WindowsARMTargetInfo(Triple) {
4743 TheCXXABI.set(TargetCXXABI::Microsoft);
4744 }
4745
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4746 void getTargetDefines(const LangOptions &Opts,
4747 MacroBuilder &Builder) const override {
4748 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4749 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4750 }
4751 };
4752
4753 class DarwinARMTargetInfo :
4754 public DarwinTargetInfo<ARMleTargetInfo> {
4755 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const4756 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4757 MacroBuilder &Builder) const override {
4758 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4759 }
4760
4761 public:
DarwinARMTargetInfo(const llvm::Triple & Triple)4762 DarwinARMTargetInfo(const llvm::Triple &Triple)
4763 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4764 HasAlignMac68kSupport = true;
4765 // iOS always has 64-bit atomic instructions.
4766 // FIXME: This should be based off of the target features in
4767 // ARMleTargetInfo.
4768 MaxAtomicInlineWidth = 64;
4769
4770 // Darwin on iOS uses a variant of the ARM C++ ABI.
4771 TheCXXABI.set(TargetCXXABI::iOS);
4772 }
4773 };
4774
4775 class AArch64TargetInfo : public TargetInfo {
4776 virtual void setDescriptionString() = 0;
4777 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4778 static const char *const GCCRegNames[];
4779
4780 enum FPUModeEnum {
4781 FPUMode,
4782 NeonMode
4783 };
4784
4785 unsigned FPU;
4786 unsigned CRC;
4787 unsigned Crypto;
4788
4789 static const Builtin::Info BuiltinInfo[];
4790
4791 std::string ABI;
4792
4793 public:
AArch64TargetInfo(const llvm::Triple & Triple)4794 AArch64TargetInfo(const llvm::Triple &Triple)
4795 : TargetInfo(Triple), ABI("aapcs") {
4796
4797 if (getTriple().getOS() == llvm::Triple::NetBSD) {
4798 WCharType = SignedInt;
4799
4800 // NetBSD apparently prefers consistency across ARM targets to consistency
4801 // across 64-bit targets.
4802 Int64Type = SignedLongLong;
4803 IntMaxType = SignedLongLong;
4804 } else {
4805 WCharType = UnsignedInt;
4806 Int64Type = SignedLong;
4807 IntMaxType = SignedLong;
4808 }
4809
4810 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4811 MaxVectorAlign = 128;
4812 RegParmMax = 8;
4813 MaxAtomicInlineWidth = 128;
4814 MaxAtomicPromoteWidth = 128;
4815
4816 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
4817 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4818
4819 // {} in inline assembly are neon specifiers, not assembly variant
4820 // specifiers.
4821 NoAsmVariants = true;
4822
4823 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
4824 // contributes to the alignment of the containing aggregate in the same way
4825 // a plain (non bit-field) member of that type would, without exception for
4826 // zero-sized or anonymous bit-fields."
4827 UseBitFieldTypeAlignment = true;
4828 UseZeroLengthBitfieldAlignment = true;
4829
4830 // AArch64 targets default to using the ARM C++ ABI.
4831 TheCXXABI.set(TargetCXXABI::GenericAArch64);
4832 }
4833
getABI() const4834 StringRef getABI() const override { return ABI; }
setABI(const std::string & Name)4835 bool setABI(const std::string &Name) override {
4836 if (Name != "aapcs" && Name != "darwinpcs")
4837 return false;
4838
4839 ABI = Name;
4840 return true;
4841 }
4842
setCPU(const std::string & Name)4843 bool setCPU(const std::string &Name) override {
4844 bool CPUKnown = llvm::StringSwitch<bool>(Name)
4845 .Case("generic", true)
4846 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
4847 .Case("cyclone", true)
4848 .Default(false);
4849 return CPUKnown;
4850 }
4851
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const4852 void getTargetDefines(const LangOptions &Opts,
4853 MacroBuilder &Builder) const override {
4854 // Target identification.
4855 Builder.defineMacro("__aarch64__");
4856
4857 // Target properties.
4858 Builder.defineMacro("_LP64");
4859 Builder.defineMacro("__LP64__");
4860
4861 // ACLE predefines. Many can only have one possible value on v8 AArch64.
4862 Builder.defineMacro("__ARM_ACLE", "200");
4863 Builder.defineMacro("__ARM_ARCH", "8");
4864 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4865
4866 Builder.defineMacro("__ARM_64BIT_STATE");
4867 Builder.defineMacro("__ARM_PCS_AAPCS64");
4868 Builder.defineMacro("__ARM_ARCH_ISA_A64");
4869
4870 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4871 Builder.defineMacro("__ARM_FEATURE_CLZ");
4872 Builder.defineMacro("__ARM_FEATURE_FMA");
4873 Builder.defineMacro("__ARM_FEATURE_DIV");
4874 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4875 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
4876 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4877 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4878
4879 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4880
4881 // 0xe implies support for half, single and double precision operations.
4882 Builder.defineMacro("__ARM_FP", "0xe");
4883
4884 // PCS specifies this for SysV variants, which is all we support. Other ABIs
4885 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4886 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4887
4888 if (Opts.FastMath || Opts.FiniteMathOnly)
4889 Builder.defineMacro("__ARM_FP_FAST");
4890
4891 if (Opts.C99 && !Opts.Freestanding)
4892 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4893
4894 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4895
4896 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4897 Opts.ShortEnums ? "1" : "4");
4898
4899 if (FPU == NeonMode) {
4900 Builder.defineMacro("__ARM_NEON");
4901 // 64-bit NEON supports half, single and double precision operations.
4902 Builder.defineMacro("__ARM_NEON_FP", "0xe");
4903 }
4904
4905 if (CRC)
4906 Builder.defineMacro("__ARM_FEATURE_CRC32");
4907
4908 if (Crypto)
4909 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4910 }
4911
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const4912 void getTargetBuiltins(const Builtin::Info *&Records,
4913 unsigned &NumRecords) const override {
4914 Records = BuiltinInfo;
4915 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4916 }
4917
hasFeature(StringRef Feature) const4918 bool hasFeature(StringRef Feature) const override {
4919 return Feature == "aarch64" ||
4920 Feature == "arm64" ||
4921 (Feature == "neon" && FPU == NeonMode);
4922 }
4923
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)4924 bool handleTargetFeatures(std::vector<std::string> &Features,
4925 DiagnosticsEngine &Diags) override {
4926 FPU = FPUMode;
4927 CRC = 0;
4928 Crypto = 0;
4929 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4930 if (Features[i] == "+neon")
4931 FPU = NeonMode;
4932 if (Features[i] == "+crc")
4933 CRC = 1;
4934 if (Features[i] == "+crypto")
4935 Crypto = 1;
4936 }
4937
4938 setDescriptionString();
4939
4940 return true;
4941 }
4942
isCLZForZeroUndef() const4943 bool isCLZForZeroUndef() const override { return false; }
4944
getBuiltinVaListKind() const4945 BuiltinVaListKind getBuiltinVaListKind() const override {
4946 return TargetInfo::AArch64ABIBuiltinVaList;
4947 }
4948
4949 void getGCCRegNames(const char *const *&Names,
4950 unsigned &NumNames) const override;
4951 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4952 unsigned &NumAliases) const override;
4953
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const4954 bool validateAsmConstraint(const char *&Name,
4955 TargetInfo::ConstraintInfo &Info) const override {
4956 switch (*Name) {
4957 default:
4958 return false;
4959 case 'w': // Floating point and SIMD registers (V0-V31)
4960 Info.setAllowsRegister();
4961 return true;
4962 case 'I': // Constant that can be used with an ADD instruction
4963 case 'J': // Constant that can be used with a SUB instruction
4964 case 'K': // Constant that can be used with a 32-bit logical instruction
4965 case 'L': // Constant that can be used with a 64-bit logical instruction
4966 case 'M': // Constant that can be used as a 32-bit MOV immediate
4967 case 'N': // Constant that can be used as a 64-bit MOV immediate
4968 case 'Y': // Floating point constant zero
4969 case 'Z': // Integer constant zero
4970 return true;
4971 case 'Q': // A memory reference with base register and no offset
4972 Info.setAllowsMemory();
4973 return true;
4974 case 'S': // A symbolic address
4975 Info.setAllowsRegister();
4976 return true;
4977 case 'U':
4978 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
4979 // Utf: A memory address suitable for ldp/stp in TF mode.
4980 // Usa: An absolute symbolic address.
4981 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
4982 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
4983 case 'z': // Zero register, wzr or xzr
4984 Info.setAllowsRegister();
4985 return true;
4986 case 'x': // Floating point and SIMD registers (V0-V15)
4987 Info.setAllowsRegister();
4988 return true;
4989 }
4990 return false;
4991 }
4992
4993 bool
validateConstraintModifier(StringRef Constraint,char Modifier,unsigned Size,std::string & SuggestedModifier) const4994 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4995 std::string &SuggestedModifier) const override {
4996 // Strip off constraint modifiers.
4997 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4998 Constraint = Constraint.substr(1);
4999
5000 switch (Constraint[0]) {
5001 default:
5002 return true;
5003 case 'z':
5004 case 'r': {
5005 switch (Modifier) {
5006 case 'x':
5007 case 'w':
5008 // For now assume that the person knows what they're
5009 // doing with the modifier.
5010 return true;
5011 default:
5012 // By default an 'r' constraint will be in the 'x'
5013 // registers.
5014 if (Size == 64)
5015 return true;
5016
5017 SuggestedModifier = "w";
5018 return false;
5019 }
5020 }
5021 }
5022 }
5023
getClobbers() const5024 const char *getClobbers() const override { return ""; }
5025
getEHDataRegisterNumber(unsigned RegNo) const5026 int getEHDataRegisterNumber(unsigned RegNo) const override {
5027 if (RegNo == 0)
5028 return 0;
5029 if (RegNo == 1)
5030 return 1;
5031 return -1;
5032 }
5033 };
5034
5035 const char *const AArch64TargetInfo::GCCRegNames[] = {
5036 // 32-bit Integer registers
5037 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
5038 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5039 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5040
5041 // 64-bit Integer registers
5042 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
5043 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5044 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
5045
5046 // 32-bit floating point regsisters
5047 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
5048 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5049 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5050
5051 // 64-bit floating point regsisters
5052 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
5053 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5054 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5055
5056 // Vector registers
5057 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
5058 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5059 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5060 };
5061
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5062 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
5063 unsigned &NumNames) const {
5064 Names = GCCRegNames;
5065 NumNames = llvm::array_lengthof(GCCRegNames);
5066 }
5067
5068 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5069 { { "w31" }, "wsp" },
5070 { { "x29" }, "fp" },
5071 { { "x30" }, "lr" },
5072 { { "x31" }, "sp" },
5073 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5074 // don't want to substitute one of these for a different-sized one.
5075 };
5076
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const5077 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5078 unsigned &NumAliases) const {
5079 Aliases = GCCRegAliases;
5080 NumAliases = llvm::array_lengthof(GCCRegAliases);
5081 }
5082
5083 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5084 #define BUILTIN(ID, TYPE, ATTRS) \
5085 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5086 #include "clang/Basic/BuiltinsNEON.def"
5087
5088 #define BUILTIN(ID, TYPE, ATTRS) \
5089 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5090 #include "clang/Basic/BuiltinsAArch64.def"
5091 };
5092
5093 class AArch64leTargetInfo : public AArch64TargetInfo {
setDescriptionString()5094 void setDescriptionString() override {
5095 if (getTriple().isOSBinFormatMachO())
5096 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
5097 else
5098 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
5099 }
5100
5101 public:
AArch64leTargetInfo(const llvm::Triple & Triple)5102 AArch64leTargetInfo(const llvm::Triple &Triple)
5103 : AArch64TargetInfo(Triple) {
5104 BigEndian = false;
5105 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5106 void getTargetDefines(const LangOptions &Opts,
5107 MacroBuilder &Builder) const override {
5108 Builder.defineMacro("__AARCH64EL__");
5109 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5110 }
5111 };
5112
5113 class AArch64beTargetInfo : public AArch64TargetInfo {
setDescriptionString()5114 void setDescriptionString() override {
5115 assert(!getTriple().isOSBinFormatMachO());
5116 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
5117 }
5118
5119 public:
AArch64beTargetInfo(const llvm::Triple & Triple)5120 AArch64beTargetInfo(const llvm::Triple &Triple)
5121 : AArch64TargetInfo(Triple) { }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5122 void getTargetDefines(const LangOptions &Opts,
5123 MacroBuilder &Builder) const override {
5124 Builder.defineMacro("__AARCH64EB__");
5125 Builder.defineMacro("__AARCH_BIG_ENDIAN");
5126 Builder.defineMacro("__ARM_BIG_ENDIAN");
5127 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5128 }
5129 };
5130
5131 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5132 protected:
getOSDefines(const LangOptions & Opts,const llvm::Triple & Triple,MacroBuilder & Builder) const5133 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5134 MacroBuilder &Builder) const override {
5135 Builder.defineMacro("__AARCH64_SIMD__");
5136 Builder.defineMacro("__ARM64_ARCH_8__");
5137 Builder.defineMacro("__ARM_NEON__");
5138 Builder.defineMacro("__LITTLE_ENDIAN__");
5139 Builder.defineMacro("__REGISTER_PREFIX__", "");
5140 Builder.defineMacro("__arm64", "1");
5141 Builder.defineMacro("__arm64__", "1");
5142
5143 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5144 }
5145
5146 public:
DarwinAArch64TargetInfo(const llvm::Triple & Triple)5147 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5148 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5149 Int64Type = SignedLongLong;
5150 WCharType = SignedInt;
5151 UseSignedCharForObjCBool = false;
5152
5153 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5154 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5155
5156 TheCXXABI.set(TargetCXXABI::iOS64);
5157 }
5158
getBuiltinVaListKind() const5159 BuiltinVaListKind getBuiltinVaListKind() const override {
5160 return TargetInfo::CharPtrBuiltinVaList;
5161 }
5162 };
5163
5164 // Hexagon abstract base class
5165 class HexagonTargetInfo : public TargetInfo {
5166 static const Builtin::Info BuiltinInfo[];
5167 static const char * const GCCRegNames[];
5168 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5169 std::string CPU;
5170 public:
HexagonTargetInfo(const llvm::Triple & Triple)5171 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5172 BigEndian = false;
5173 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5174
5175 // {} in inline assembly are packet specifiers, not assembly variant
5176 // specifiers.
5177 NoAsmVariants = true;
5178 }
5179
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const5180 void getTargetBuiltins(const Builtin::Info *&Records,
5181 unsigned &NumRecords) const override {
5182 Records = BuiltinInfo;
5183 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5184 }
5185
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const5186 bool validateAsmConstraint(const char *&Name,
5187 TargetInfo::ConstraintInfo &Info) const override {
5188 return true;
5189 }
5190
5191 void getTargetDefines(const LangOptions &Opts,
5192 MacroBuilder &Builder) const override;
5193
hasFeature(StringRef Feature) const5194 bool hasFeature(StringRef Feature) const override {
5195 return Feature == "hexagon";
5196 }
5197
getBuiltinVaListKind() const5198 BuiltinVaListKind getBuiltinVaListKind() const override {
5199 return TargetInfo::CharPtrBuiltinVaList;
5200 }
5201 void getGCCRegNames(const char * const *&Names,
5202 unsigned &NumNames) const override;
5203 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5204 unsigned &NumAliases) const override;
getClobbers() const5205 const char *getClobbers() const override {
5206 return "";
5207 }
5208
getHexagonCPUSuffix(StringRef Name)5209 static const char *getHexagonCPUSuffix(StringRef Name) {
5210 return llvm::StringSwitch<const char*>(Name)
5211 .Case("hexagonv4", "4")
5212 .Case("hexagonv5", "5")
5213 .Default(nullptr);
5214 }
5215
setCPU(const std::string & Name)5216 bool setCPU(const std::string &Name) override {
5217 if (!getHexagonCPUSuffix(Name))
5218 return false;
5219
5220 CPU = Name;
5221 return true;
5222 }
5223 };
5224
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5225 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5226 MacroBuilder &Builder) const {
5227 Builder.defineMacro("qdsp6");
5228 Builder.defineMacro("__qdsp6", "1");
5229 Builder.defineMacro("__qdsp6__", "1");
5230
5231 Builder.defineMacro("hexagon");
5232 Builder.defineMacro("__hexagon", "1");
5233 Builder.defineMacro("__hexagon__", "1");
5234
5235 if(CPU == "hexagonv1") {
5236 Builder.defineMacro("__HEXAGON_V1__");
5237 Builder.defineMacro("__HEXAGON_ARCH__", "1");
5238 if(Opts.HexagonQdsp6Compat) {
5239 Builder.defineMacro("__QDSP6_V1__");
5240 Builder.defineMacro("__QDSP6_ARCH__", "1");
5241 }
5242 }
5243 else if(CPU == "hexagonv2") {
5244 Builder.defineMacro("__HEXAGON_V2__");
5245 Builder.defineMacro("__HEXAGON_ARCH__", "2");
5246 if(Opts.HexagonQdsp6Compat) {
5247 Builder.defineMacro("__QDSP6_V2__");
5248 Builder.defineMacro("__QDSP6_ARCH__", "2");
5249 }
5250 }
5251 else if(CPU == "hexagonv3") {
5252 Builder.defineMacro("__HEXAGON_V3__");
5253 Builder.defineMacro("__HEXAGON_ARCH__", "3");
5254 if(Opts.HexagonQdsp6Compat) {
5255 Builder.defineMacro("__QDSP6_V3__");
5256 Builder.defineMacro("__QDSP6_ARCH__", "3");
5257 }
5258 }
5259 else if(CPU == "hexagonv4") {
5260 Builder.defineMacro("__HEXAGON_V4__");
5261 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5262 if(Opts.HexagonQdsp6Compat) {
5263 Builder.defineMacro("__QDSP6_V4__");
5264 Builder.defineMacro("__QDSP6_ARCH__", "4");
5265 }
5266 }
5267 else if(CPU == "hexagonv5") {
5268 Builder.defineMacro("__HEXAGON_V5__");
5269 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5270 if(Opts.HexagonQdsp6Compat) {
5271 Builder.defineMacro("__QDSP6_V5__");
5272 Builder.defineMacro("__QDSP6_ARCH__", "5");
5273 }
5274 }
5275 }
5276
5277 const char * const HexagonTargetInfo::GCCRegNames[] = {
5278 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5279 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5280 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5281 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5282 "p0", "p1", "p2", "p3",
5283 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5284 };
5285
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5286 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5287 unsigned &NumNames) const {
5288 Names = GCCRegNames;
5289 NumNames = llvm::array_lengthof(GCCRegNames);
5290 }
5291
5292
5293 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5294 { { "sp" }, "r29" },
5295 { { "fp" }, "r30" },
5296 { { "lr" }, "r31" },
5297 };
5298
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const5299 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5300 unsigned &NumAliases) const {
5301 Aliases = GCCRegAliases;
5302 NumAliases = llvm::array_lengthof(GCCRegAliases);
5303 }
5304
5305
5306 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5307 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5308 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5309 ALL_LANGUAGES },
5310 #include "clang/Basic/BuiltinsHexagon.def"
5311 };
5312
5313 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5314 class SparcTargetInfo : public TargetInfo {
5315 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5316 static const char * const GCCRegNames[];
5317 bool SoftFloat;
5318 public:
SparcTargetInfo(const llvm::Triple & Triple)5319 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5320
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)5321 bool handleTargetFeatures(std::vector<std::string> &Features,
5322 DiagnosticsEngine &Diags) override {
5323 SoftFloat = false;
5324 for (unsigned i = 0, e = Features.size(); i != e; ++i)
5325 if (Features[i] == "+soft-float")
5326 SoftFloat = true;
5327 return true;
5328 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5329 void getTargetDefines(const LangOptions &Opts,
5330 MacroBuilder &Builder) const override {
5331 DefineStd(Builder, "sparc", Opts);
5332 Builder.defineMacro("__REGISTER_PREFIX__", "");
5333
5334 if (SoftFloat)
5335 Builder.defineMacro("SOFT_FLOAT", "1");
5336 }
5337
hasFeature(StringRef Feature) const5338 bool hasFeature(StringRef Feature) const override {
5339 return llvm::StringSwitch<bool>(Feature)
5340 .Case("softfloat", SoftFloat)
5341 .Case("sparc", true)
5342 .Default(false);
5343 }
5344
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const5345 void getTargetBuiltins(const Builtin::Info *&Records,
5346 unsigned &NumRecords) const override {
5347 // FIXME: Implement!
5348 }
getBuiltinVaListKind() const5349 BuiltinVaListKind getBuiltinVaListKind() const override {
5350 return TargetInfo::VoidPtrBuiltinVaList;
5351 }
5352 void getGCCRegNames(const char * const *&Names,
5353 unsigned &NumNames) const override;
5354 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5355 unsigned &NumAliases) const override;
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & info) const5356 bool validateAsmConstraint(const char *&Name,
5357 TargetInfo::ConstraintInfo &info) const override {
5358 // FIXME: Implement!
5359 switch (*Name) {
5360 case 'I': // Signed 13-bit constant
5361 case 'J': // Zero
5362 case 'K': // 32-bit constant with the low 12 bits clear
5363 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5364 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5365 case 'N': // Same as 'K' but zext (required for SIMode)
5366 case 'O': // The constant 4096
5367 return true;
5368 }
5369 return false;
5370 }
getClobbers() const5371 const char *getClobbers() const override {
5372 // FIXME: Implement!
5373 return "";
5374 }
5375 };
5376
5377 const char * const SparcTargetInfo::GCCRegNames[] = {
5378 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5379 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5380 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5381 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5382 };
5383
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5384 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5385 unsigned &NumNames) const {
5386 Names = GCCRegNames;
5387 NumNames = llvm::array_lengthof(GCCRegNames);
5388 }
5389
5390 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5391 { { "g0" }, "r0" },
5392 { { "g1" }, "r1" },
5393 { { "g2" }, "r2" },
5394 { { "g3" }, "r3" },
5395 { { "g4" }, "r4" },
5396 { { "g5" }, "r5" },
5397 { { "g6" }, "r6" },
5398 { { "g7" }, "r7" },
5399 { { "o0" }, "r8" },
5400 { { "o1" }, "r9" },
5401 { { "o2" }, "r10" },
5402 { { "o3" }, "r11" },
5403 { { "o4" }, "r12" },
5404 { { "o5" }, "r13" },
5405 { { "o6", "sp" }, "r14" },
5406 { { "o7" }, "r15" },
5407 { { "l0" }, "r16" },
5408 { { "l1" }, "r17" },
5409 { { "l2" }, "r18" },
5410 { { "l3" }, "r19" },
5411 { { "l4" }, "r20" },
5412 { { "l5" }, "r21" },
5413 { { "l6" }, "r22" },
5414 { { "l7" }, "r23" },
5415 { { "i0" }, "r24" },
5416 { { "i1" }, "r25" },
5417 { { "i2" }, "r26" },
5418 { { "i3" }, "r27" },
5419 { { "i4" }, "r28" },
5420 { { "i5" }, "r29" },
5421 { { "i6", "fp" }, "r30" },
5422 { { "i7" }, "r31" },
5423 };
5424
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const5425 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5426 unsigned &NumAliases) const {
5427 Aliases = GCCRegAliases;
5428 NumAliases = llvm::array_lengthof(GCCRegAliases);
5429 }
5430
5431 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5432 class SparcV8TargetInfo : public SparcTargetInfo {
5433 public:
SparcV8TargetInfo(const llvm::Triple & Triple)5434 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5435 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5436 }
5437
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5438 void getTargetDefines(const LangOptions &Opts,
5439 MacroBuilder &Builder) const override {
5440 SparcTargetInfo::getTargetDefines(Opts, Builder);
5441 Builder.defineMacro("__sparcv8");
5442 }
5443 };
5444
5445 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5446 class SparcV9TargetInfo : public SparcTargetInfo {
5447 public:
SparcV9TargetInfo(const llvm::Triple & Triple)5448 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5449 // FIXME: Support Sparc quad-precision long double?
5450 DescriptionString = "E-m:e-i64:64-n32:64-S128";
5451 // This is an LP64 platform.
5452 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5453
5454 // OpenBSD uses long long for int64_t and intmax_t.
5455 if (getTriple().getOS() == llvm::Triple::OpenBSD)
5456 IntMaxType = SignedLongLong;
5457 else
5458 IntMaxType = SignedLong;
5459 Int64Type = IntMaxType;
5460
5461 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5462 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5463 LongDoubleWidth = 128;
5464 LongDoubleAlign = 128;
5465 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5466 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5467 }
5468
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5469 void getTargetDefines(const LangOptions &Opts,
5470 MacroBuilder &Builder) const override {
5471 SparcTargetInfo::getTargetDefines(Opts, Builder);
5472 Builder.defineMacro("__sparcv9");
5473 Builder.defineMacro("__arch64__");
5474 // Solaris doesn't need these variants, but the BSDs do.
5475 if (getTriple().getOS() != llvm::Triple::Solaris) {
5476 Builder.defineMacro("__sparc64__");
5477 Builder.defineMacro("__sparc_v9__");
5478 Builder.defineMacro("__sparcv9__");
5479 }
5480 }
5481
setCPU(const std::string & Name)5482 bool setCPU(const std::string &Name) override {
5483 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5484 .Case("v9", true)
5485 .Case("ultrasparc", true)
5486 .Case("ultrasparc3", true)
5487 .Case("niagara", true)
5488 .Case("niagara2", true)
5489 .Case("niagara3", true)
5490 .Case("niagara4", true)
5491 .Default(false);
5492
5493 // No need to store the CPU yet. There aren't any CPU-specific
5494 // macros to define.
5495 return CPUKnown;
5496 }
5497 };
5498
5499 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5500 public:
SolarisSparcV8TargetInfo(const llvm::Triple & Triple)5501 SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5502 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5503 SizeType = UnsignedInt;
5504 PtrDiffType = SignedInt;
5505 }
5506 };
5507
5508 class SystemZTargetInfo : public TargetInfo {
5509 static const Builtin::Info BuiltinInfo[];
5510 static const char *const GCCRegNames[];
5511 std::string CPU;
5512 bool HasTransactionalExecution;
5513
5514 public:
SystemZTargetInfo(const llvm::Triple & Triple)5515 SystemZTargetInfo(const llvm::Triple &Triple)
5516 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false) {
5517 IntMaxType = SignedLong;
5518 Int64Type = SignedLong;
5519 TLSSupported = true;
5520 IntWidth = IntAlign = 32;
5521 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5522 PointerWidth = PointerAlign = 64;
5523 LongDoubleWidth = 128;
5524 LongDoubleAlign = 64;
5525 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5526 MinGlobalAlign = 16;
5527 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5528 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5529 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5530 void getTargetDefines(const LangOptions &Opts,
5531 MacroBuilder &Builder) const override {
5532 Builder.defineMacro("__s390__");
5533 Builder.defineMacro("__s390x__");
5534 Builder.defineMacro("__zarch__");
5535 Builder.defineMacro("__LONG_DOUBLE_128__");
5536 if (HasTransactionalExecution)
5537 Builder.defineMacro("__HTM__");
5538 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const5539 void getTargetBuiltins(const Builtin::Info *&Records,
5540 unsigned &NumRecords) const override {
5541 Records = BuiltinInfo;
5542 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin;
5543 }
5544
5545 void getGCCRegNames(const char *const *&Names,
5546 unsigned &NumNames) const override;
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const5547 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5548 unsigned &NumAliases) const override {
5549 // No aliases.
5550 Aliases = nullptr;
5551 NumAliases = 0;
5552 }
5553 bool validateAsmConstraint(const char *&Name,
5554 TargetInfo::ConstraintInfo &info) const override;
getClobbers() const5555 const char *getClobbers() const override {
5556 // FIXME: Is this really right?
5557 return "";
5558 }
getBuiltinVaListKind() const5559 BuiltinVaListKind getBuiltinVaListKind() const override {
5560 return TargetInfo::SystemZBuiltinVaList;
5561 }
setCPU(const std::string & Name)5562 bool setCPU(const std::string &Name) override {
5563 CPU = Name;
5564 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5565 .Case("z10", true)
5566 .Case("z196", true)
5567 .Case("zEC12", true)
5568 .Default(false);
5569
5570 return CPUKnown;
5571 }
getDefaultFeatures(llvm::StringMap<bool> & Features) const5572 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5573 if (CPU == "zEC12")
5574 Features["transactional-execution"] = true;
5575 }
5576
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)5577 bool handleTargetFeatures(std::vector<std::string> &Features,
5578 DiagnosticsEngine &Diags) override {
5579 HasTransactionalExecution = false;
5580 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
5581 if (Features[i] == "+transactional-execution")
5582 HasTransactionalExecution = true;
5583 }
5584 return true;
5585 }
5586
hasFeature(StringRef Feature) const5587 bool hasFeature(StringRef Feature) const override {
5588 return llvm::StringSwitch<bool>(Feature)
5589 .Case("systemz", true)
5590 .Case("htm", HasTransactionalExecution)
5591 .Default(false);
5592 }
5593 };
5594
5595 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
5596 #define BUILTIN(ID, TYPE, ATTRS) \
5597 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5598 #include "clang/Basic/BuiltinsSystemZ.def"
5599 };
5600
5601 const char *const SystemZTargetInfo::GCCRegNames[] = {
5602 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5603 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5604 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
5605 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
5606 };
5607
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5608 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5609 unsigned &NumNames) const {
5610 Names = GCCRegNames;
5611 NumNames = llvm::array_lengthof(GCCRegNames);
5612 }
5613
5614 bool SystemZTargetInfo::
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const5615 validateAsmConstraint(const char *&Name,
5616 TargetInfo::ConstraintInfo &Info) const {
5617 switch (*Name) {
5618 default:
5619 return false;
5620
5621 case 'a': // Address register
5622 case 'd': // Data register (equivalent to 'r')
5623 case 'f': // Floating-point register
5624 Info.setAllowsRegister();
5625 return true;
5626
5627 case 'I': // Unsigned 8-bit constant
5628 case 'J': // Unsigned 12-bit constant
5629 case 'K': // Signed 16-bit constant
5630 case 'L': // Signed 20-bit displacement (on all targets we support)
5631 case 'M': // 0x7fffffff
5632 return true;
5633
5634 case 'Q': // Memory with base and unsigned 12-bit displacement
5635 case 'R': // Likewise, plus an index
5636 case 'S': // Memory with base and signed 20-bit displacement
5637 case 'T': // Likewise, plus an index
5638 Info.setAllowsMemory();
5639 return true;
5640 }
5641 }
5642
5643 class MSP430TargetInfo : public TargetInfo {
5644 static const char * const GCCRegNames[];
5645 public:
MSP430TargetInfo(const llvm::Triple & Triple)5646 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5647 BigEndian = false;
5648 TLSSupported = false;
5649 IntWidth = 16; IntAlign = 16;
5650 LongWidth = 32; LongLongWidth = 64;
5651 LongAlign = LongLongAlign = 16;
5652 PointerWidth = 16; PointerAlign = 16;
5653 SuitableAlign = 16;
5654 SizeType = UnsignedInt;
5655 IntMaxType = SignedLongLong;
5656 IntPtrType = SignedInt;
5657 PtrDiffType = SignedInt;
5658 SigAtomicType = SignedLong;
5659 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5660 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5661 void getTargetDefines(const LangOptions &Opts,
5662 MacroBuilder &Builder) const override {
5663 Builder.defineMacro("MSP430");
5664 Builder.defineMacro("__MSP430__");
5665 // FIXME: defines for different 'flavours' of MCU
5666 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const5667 void getTargetBuiltins(const Builtin::Info *&Records,
5668 unsigned &NumRecords) const override {
5669 // FIXME: Implement.
5670 Records = nullptr;
5671 NumRecords = 0;
5672 }
hasFeature(StringRef Feature) const5673 bool hasFeature(StringRef Feature) const override {
5674 return Feature == "msp430";
5675 }
5676 void getGCCRegNames(const char * const *&Names,
5677 unsigned &NumNames) const override;
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const5678 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5679 unsigned &NumAliases) const override {
5680 // No aliases.
5681 Aliases = nullptr;
5682 NumAliases = 0;
5683 }
5684 bool
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & info) const5685 validateAsmConstraint(const char *&Name,
5686 TargetInfo::ConstraintInfo &info) const override {
5687 // FIXME: implement
5688 switch (*Name) {
5689 case 'K': // the constant 1
5690 case 'L': // constant -1^20 .. 1^19
5691 case 'M': // constant 1-4:
5692 return true;
5693 }
5694 // No target constraints for now.
5695 return false;
5696 }
getClobbers() const5697 const char *getClobbers() const override {
5698 // FIXME: Is this really right?
5699 return "";
5700 }
getBuiltinVaListKind() const5701 BuiltinVaListKind getBuiltinVaListKind() const override {
5702 // FIXME: implement
5703 return TargetInfo::CharPtrBuiltinVaList;
5704 }
5705 };
5706
5707 const char * const MSP430TargetInfo::GCCRegNames[] = {
5708 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5709 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5710 };
5711
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5712 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5713 unsigned &NumNames) const {
5714 Names = GCCRegNames;
5715 NumNames = llvm::array_lengthof(GCCRegNames);
5716 }
5717
5718 // LLVM and Clang cannot be used directly to output native binaries for
5719 // target, but is used to compile C code to llvm bitcode with correct
5720 // type and alignment information.
5721 //
5722 // TCE uses the llvm bitcode as input and uses it for generating customized
5723 // target processor and program binary. TCE co-design environment is
5724 // publicly available in http://tce.cs.tut.fi
5725
5726 static const unsigned TCEOpenCLAddrSpaceMap[] = {
5727 3, // opencl_global
5728 4, // opencl_local
5729 5, // opencl_constant
5730 // FIXME: generic has to be added to the target
5731 0, // opencl_generic
5732 0, // cuda_device
5733 0, // cuda_constant
5734 0 // cuda_shared
5735 };
5736
5737 class TCETargetInfo : public TargetInfo{
5738 public:
TCETargetInfo(const llvm::Triple & Triple)5739 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5740 TLSSupported = false;
5741 IntWidth = 32;
5742 LongWidth = LongLongWidth = 32;
5743 PointerWidth = 32;
5744 IntAlign = 32;
5745 LongAlign = LongLongAlign = 32;
5746 PointerAlign = 32;
5747 SuitableAlign = 32;
5748 SizeType = UnsignedInt;
5749 IntMaxType = SignedLong;
5750 IntPtrType = SignedInt;
5751 PtrDiffType = SignedInt;
5752 FloatWidth = 32;
5753 FloatAlign = 32;
5754 DoubleWidth = 32;
5755 DoubleAlign = 32;
5756 LongDoubleWidth = 32;
5757 LongDoubleAlign = 32;
5758 FloatFormat = &llvm::APFloat::IEEEsingle;
5759 DoubleFormat = &llvm::APFloat::IEEEsingle;
5760 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5761 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5762 "-f64:32-v64:32-v128:32-a:0:32-n32";
5763 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5764 UseAddrSpaceMapMangling = true;
5765 }
5766
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5767 void getTargetDefines(const LangOptions &Opts,
5768 MacroBuilder &Builder) const override {
5769 DefineStd(Builder, "tce", Opts);
5770 Builder.defineMacro("__TCE__");
5771 Builder.defineMacro("__TCE_V1__");
5772 }
hasFeature(StringRef Feature) const5773 bool hasFeature(StringRef Feature) const override {
5774 return Feature == "tce";
5775 }
5776
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const5777 void getTargetBuiltins(const Builtin::Info *&Records,
5778 unsigned &NumRecords) const override {}
getClobbers() const5779 const char *getClobbers() const override {
5780 return "";
5781 }
getBuiltinVaListKind() const5782 BuiltinVaListKind getBuiltinVaListKind() const override {
5783 return TargetInfo::VoidPtrBuiltinVaList;
5784 }
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5785 void getGCCRegNames(const char * const *&Names,
5786 unsigned &NumNames) const override {}
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & info) const5787 bool validateAsmConstraint(const char *&Name,
5788 TargetInfo::ConstraintInfo &info) const override{
5789 return true;
5790 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const5791 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5792 unsigned &NumAliases) const override {}
5793 };
5794
5795 class MipsTargetInfoBase : public TargetInfo {
5796 virtual void setDescriptionString() = 0;
5797
5798 static const Builtin::Info BuiltinInfo[];
5799 std::string CPU;
5800 bool IsMips16;
5801 bool IsMicromips;
5802 bool IsNan2008;
5803 bool IsSingleFloat;
5804 enum MipsFloatABI {
5805 HardFloat, SoftFloat
5806 } FloatABI;
5807 enum DspRevEnum {
5808 NoDSP, DSP1, DSP2
5809 } DspRev;
5810 bool HasMSA;
5811
5812 protected:
5813 bool HasFP64;
5814 std::string ABI;
5815
5816 public:
MipsTargetInfoBase(const llvm::Triple & Triple,const std::string & ABIStr,const std::string & CPUStr)5817 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5818 const std::string &CPUStr)
5819 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5820 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5821 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
5822 TheCXXABI.set(TargetCXXABI::GenericMIPS);
5823 }
5824
isNaN2008Default() const5825 bool isNaN2008Default() const {
5826 return CPU == "mips32r6" || CPU == "mips64r6";
5827 }
5828
isFP64Default() const5829 bool isFP64Default() const {
5830 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5831 }
5832
isNan2008() const5833 bool isNan2008() const override {
5834 return IsNan2008;
5835 }
5836
getABI() const5837 StringRef getABI() const override { return ABI; }
setCPU(const std::string & Name)5838 bool setCPU(const std::string &Name) override {
5839 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5840 getTriple().getArch() == llvm::Triple::mipsel;
5841 CPU = Name;
5842 return llvm::StringSwitch<bool>(Name)
5843 .Case("mips1", IsMips32)
5844 .Case("mips2", IsMips32)
5845 .Case("mips3", true)
5846 .Case("mips4", true)
5847 .Case("mips5", true)
5848 .Case("mips32", IsMips32)
5849 .Case("mips32r2", IsMips32)
5850 .Case("mips32r3", IsMips32)
5851 .Case("mips32r5", IsMips32)
5852 .Case("mips32r6", IsMips32)
5853 .Case("mips64", true)
5854 .Case("mips64r2", true)
5855 .Case("mips64r3", true)
5856 .Case("mips64r5", true)
5857 .Case("mips64r6", true)
5858 .Case("octeon", true)
5859 .Default(false);
5860 }
getCPU() const5861 const std::string& getCPU() const { return CPU; }
getDefaultFeatures(llvm::StringMap<bool> & Features) const5862 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5863 if (CPU == "octeon")
5864 Features["mips64r2"] = Features["cnmips"] = true;
5865 else
5866 Features[CPU] = true;
5867 }
5868
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const5869 void getTargetDefines(const LangOptions &Opts,
5870 MacroBuilder &Builder) const override {
5871 Builder.defineMacro("__mips__");
5872 Builder.defineMacro("_mips");
5873 if (Opts.GNUMode)
5874 Builder.defineMacro("mips");
5875
5876 Builder.defineMacro("__REGISTER_PREFIX__", "");
5877
5878 switch (FloatABI) {
5879 case HardFloat:
5880 Builder.defineMacro("__mips_hard_float", Twine(1));
5881 break;
5882 case SoftFloat:
5883 Builder.defineMacro("__mips_soft_float", Twine(1));
5884 break;
5885 }
5886
5887 if (IsSingleFloat)
5888 Builder.defineMacro("__mips_single_float", Twine(1));
5889
5890 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5891 Builder.defineMacro("_MIPS_FPSET",
5892 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5893
5894 if (IsMips16)
5895 Builder.defineMacro("__mips16", Twine(1));
5896
5897 if (IsMicromips)
5898 Builder.defineMacro("__mips_micromips", Twine(1));
5899
5900 if (IsNan2008)
5901 Builder.defineMacro("__mips_nan2008", Twine(1));
5902
5903 switch (DspRev) {
5904 default:
5905 break;
5906 case DSP1:
5907 Builder.defineMacro("__mips_dsp_rev", Twine(1));
5908 Builder.defineMacro("__mips_dsp", Twine(1));
5909 break;
5910 case DSP2:
5911 Builder.defineMacro("__mips_dsp_rev", Twine(2));
5912 Builder.defineMacro("__mips_dspr2", Twine(1));
5913 Builder.defineMacro("__mips_dsp", Twine(1));
5914 break;
5915 }
5916
5917 if (HasMSA)
5918 Builder.defineMacro("__mips_msa", Twine(1));
5919
5920 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5921 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5922 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5923
5924 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5925 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5926 }
5927
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const5928 void getTargetBuiltins(const Builtin::Info *&Records,
5929 unsigned &NumRecords) const override {
5930 Records = BuiltinInfo;
5931 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5932 }
hasFeature(StringRef Feature) const5933 bool hasFeature(StringRef Feature) const override {
5934 return llvm::StringSwitch<bool>(Feature)
5935 .Case("mips", true)
5936 .Case("fp64", HasFP64)
5937 .Default(false);
5938 }
getBuiltinVaListKind() const5939 BuiltinVaListKind getBuiltinVaListKind() const override {
5940 return TargetInfo::VoidPtrBuiltinVaList;
5941 }
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const5942 void getGCCRegNames(const char * const *&Names,
5943 unsigned &NumNames) const override {
5944 static const char *const GCCRegNames[] = {
5945 // CPU register names
5946 // Must match second column of GCCRegAliases
5947 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
5948 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
5949 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
5950 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
5951 // Floating point register names
5952 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
5953 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5954 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5955 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5956 // Hi/lo and condition register names
5957 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5958 "$fcc5","$fcc6","$fcc7",
5959 // MSA register names
5960 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
5961 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5962 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5963 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5964 // MSA control register names
5965 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5966 "$msarequest", "$msamap", "$msaunmap"
5967 };
5968 Names = GCCRegNames;
5969 NumNames = llvm::array_lengthof(GCCRegNames);
5970 }
5971 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5972 unsigned &NumAliases) const override = 0;
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const5973 bool validateAsmConstraint(const char *&Name,
5974 TargetInfo::ConstraintInfo &Info) const override {
5975 switch (*Name) {
5976 default:
5977 return false;
5978 case 'r': // CPU registers.
5979 case 'd': // Equivalent to "r" unless generating MIPS16 code.
5980 case 'y': // Equivalent to "r", backward compatibility only.
5981 case 'f': // floating-point registers.
5982 case 'c': // $25 for indirect jumps
5983 case 'l': // lo register
5984 case 'x': // hilo register pair
5985 Info.setAllowsRegister();
5986 return true;
5987 case 'I': // Signed 16-bit constant
5988 case 'J': // Integer 0
5989 case 'K': // Unsigned 16-bit constant
5990 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
5991 case 'M': // Constants not loadable via lui, addiu, or ori
5992 case 'N': // Constant -1 to -65535
5993 case 'O': // A signed 15-bit constant
5994 case 'P': // A constant between 1 go 65535
5995 return true;
5996 case 'R': // An address that can be used in a non-macro load or store
5997 Info.setAllowsMemory();
5998 return true;
5999 case 'Z':
6000 if (Name[1] == 'C') { // An address usable by ll, and sc.
6001 Info.setAllowsMemory();
6002 Name++; // Skip over 'Z'.
6003 return true;
6004 }
6005 return false;
6006 }
6007 }
6008
convertConstraint(const char * & Constraint) const6009 std::string convertConstraint(const char *&Constraint) const override {
6010 std::string R;
6011 switch (*Constraint) {
6012 case 'Z': // Two-character constraint; add "^" hint for later parsing.
6013 if (Constraint[1] == 'C') {
6014 R = std::string("^") + std::string(Constraint, 2);
6015 Constraint++;
6016 return R;
6017 }
6018 break;
6019 }
6020 return TargetInfo::convertConstraint(Constraint);
6021 }
6022
getClobbers() const6023 const char *getClobbers() const override {
6024 // In GCC, $1 is not widely used in generated code (it's used only in a few
6025 // specific situations), so there is no real need for users to add it to
6026 // the clobbers list if they want to use it in their inline assembly code.
6027 //
6028 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
6029 // code generation, so using it in inline assembly without adding it to the
6030 // clobbers list can cause conflicts between the inline assembly code and
6031 // the surrounding generated code.
6032 //
6033 // Another problem is that LLVM is allowed to choose $1 for inline assembly
6034 // operands, which will conflict with the ".set at" assembler option (which
6035 // we use only for inline assembly, in order to maintain compatibility with
6036 // GCC) and will also conflict with the user's usage of $1.
6037 //
6038 // The easiest way to avoid these conflicts and keep $1 as an allocatable
6039 // register for generated code is to automatically clobber $1 for all inline
6040 // assembly code.
6041 //
6042 // FIXME: We should automatically clobber $1 only for inline assembly code
6043 // which actually uses it. This would allow LLVM to use $1 for inline
6044 // assembly operands if the user's assembly code doesn't use it.
6045 return "~{$1}";
6046 }
6047
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)6048 bool handleTargetFeatures(std::vector<std::string> &Features,
6049 DiagnosticsEngine &Diags) override {
6050 IsMips16 = false;
6051 IsMicromips = false;
6052 IsNan2008 = isNaN2008Default();
6053 IsSingleFloat = false;
6054 FloatABI = HardFloat;
6055 DspRev = NoDSP;
6056 HasFP64 = isFP64Default();
6057
6058 for (std::vector<std::string>::iterator it = Features.begin(),
6059 ie = Features.end(); it != ie; ++it) {
6060 if (*it == "+single-float")
6061 IsSingleFloat = true;
6062 else if (*it == "+soft-float")
6063 FloatABI = SoftFloat;
6064 else if (*it == "+mips16")
6065 IsMips16 = true;
6066 else if (*it == "+micromips")
6067 IsMicromips = true;
6068 else if (*it == "+dsp")
6069 DspRev = std::max(DspRev, DSP1);
6070 else if (*it == "+dspr2")
6071 DspRev = std::max(DspRev, DSP2);
6072 else if (*it == "+msa")
6073 HasMSA = true;
6074 else if (*it == "+fp64")
6075 HasFP64 = true;
6076 else if (*it == "-fp64")
6077 HasFP64 = false;
6078 else if (*it == "+nan2008")
6079 IsNan2008 = true;
6080 else if (*it == "-nan2008")
6081 IsNan2008 = false;
6082 }
6083
6084 // Remove front-end specific options.
6085 std::vector<std::string>::iterator it =
6086 std::find(Features.begin(), Features.end(), "+soft-float");
6087 if (it != Features.end())
6088 Features.erase(it);
6089
6090 setDescriptionString();
6091
6092 return true;
6093 }
6094
getEHDataRegisterNumber(unsigned RegNo) const6095 int getEHDataRegisterNumber(unsigned RegNo) const override {
6096 if (RegNo == 0) return 4;
6097 if (RegNo == 1) return 5;
6098 return -1;
6099 }
6100
isCLZForZeroUndef() const6101 bool isCLZForZeroUndef() const override { return false; }
6102 };
6103
6104 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
6105 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6106 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6107 ALL_LANGUAGES },
6108 #include "clang/Basic/BuiltinsMips.def"
6109 };
6110
6111 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6112 public:
Mips32TargetInfoBase(const llvm::Triple & Triple)6113 Mips32TargetInfoBase(const llvm::Triple &Triple)
6114 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6115 SizeType = UnsignedInt;
6116 PtrDiffType = SignedInt;
6117 Int64Type = SignedLongLong;
6118 IntMaxType = Int64Type;
6119 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6120 }
setABI(const std::string & Name)6121 bool setABI(const std::string &Name) override {
6122 if (Name == "o32" || Name == "eabi") {
6123 ABI = Name;
6124 return true;
6125 }
6126 return false;
6127 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6128 void getTargetDefines(const LangOptions &Opts,
6129 MacroBuilder &Builder) const override {
6130 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6131
6132 Builder.defineMacro("__mips", "32");
6133 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6134
6135 const std::string& CPUStr = getCPU();
6136 if (CPUStr == "mips32")
6137 Builder.defineMacro("__mips_isa_rev", "1");
6138 else if (CPUStr == "mips32r2")
6139 Builder.defineMacro("__mips_isa_rev", "2");
6140 else if (CPUStr == "mips32r3")
6141 Builder.defineMacro("__mips_isa_rev", "3");
6142 else if (CPUStr == "mips32r5")
6143 Builder.defineMacro("__mips_isa_rev", "5");
6144 else if (CPUStr == "mips32r6")
6145 Builder.defineMacro("__mips_isa_rev", "6");
6146
6147 if (ABI == "o32") {
6148 Builder.defineMacro("__mips_o32");
6149 Builder.defineMacro("_ABIO32", "1");
6150 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6151 }
6152 else if (ABI == "eabi")
6153 Builder.defineMacro("__mips_eabi");
6154 else
6155 llvm_unreachable("Invalid ABI for Mips32.");
6156 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const6157 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6158 unsigned &NumAliases) const override {
6159 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6160 { { "at" }, "$1" },
6161 { { "v0" }, "$2" },
6162 { { "v1" }, "$3" },
6163 { { "a0" }, "$4" },
6164 { { "a1" }, "$5" },
6165 { { "a2" }, "$6" },
6166 { { "a3" }, "$7" },
6167 { { "t0" }, "$8" },
6168 { { "t1" }, "$9" },
6169 { { "t2" }, "$10" },
6170 { { "t3" }, "$11" },
6171 { { "t4" }, "$12" },
6172 { { "t5" }, "$13" },
6173 { { "t6" }, "$14" },
6174 { { "t7" }, "$15" },
6175 { { "s0" }, "$16" },
6176 { { "s1" }, "$17" },
6177 { { "s2" }, "$18" },
6178 { { "s3" }, "$19" },
6179 { { "s4" }, "$20" },
6180 { { "s5" }, "$21" },
6181 { { "s6" }, "$22" },
6182 { { "s7" }, "$23" },
6183 { { "t8" }, "$24" },
6184 { { "t9" }, "$25" },
6185 { { "k0" }, "$26" },
6186 { { "k1" }, "$27" },
6187 { { "gp" }, "$28" },
6188 { { "sp","$sp" }, "$29" },
6189 { { "fp","$fp" }, "$30" },
6190 { { "ra" }, "$31" }
6191 };
6192 Aliases = GCCRegAliases;
6193 NumAliases = llvm::array_lengthof(GCCRegAliases);
6194 }
6195 };
6196
6197 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
setDescriptionString()6198 void setDescriptionString() override {
6199 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6200 }
6201
6202 public:
Mips32EBTargetInfo(const llvm::Triple & Triple)6203 Mips32EBTargetInfo(const llvm::Triple &Triple)
6204 : Mips32TargetInfoBase(Triple) {
6205 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6206 void getTargetDefines(const LangOptions &Opts,
6207 MacroBuilder &Builder) const override {
6208 DefineStd(Builder, "MIPSEB", Opts);
6209 Builder.defineMacro("_MIPSEB");
6210 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6211 }
6212 };
6213
6214 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
setDescriptionString()6215 void setDescriptionString() override {
6216 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6217 }
6218
6219 public:
Mips32ELTargetInfo(const llvm::Triple & Triple)6220 Mips32ELTargetInfo(const llvm::Triple &Triple)
6221 : Mips32TargetInfoBase(Triple) {
6222 BigEndian = false;
6223 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6224 void getTargetDefines(const LangOptions &Opts,
6225 MacroBuilder &Builder) const override {
6226 DefineStd(Builder, "MIPSEL", Opts);
6227 Builder.defineMacro("_MIPSEL");
6228 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6229 }
6230 };
6231
6232 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6233 public:
Mips64TargetInfoBase(const llvm::Triple & Triple)6234 Mips64TargetInfoBase(const llvm::Triple &Triple)
6235 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6236 LongDoubleWidth = LongDoubleAlign = 128;
6237 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6238 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6239 LongDoubleWidth = LongDoubleAlign = 64;
6240 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6241 }
6242 setN64ABITypes();
6243 SuitableAlign = 128;
6244 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6245 }
6246
setN64ABITypes()6247 void setN64ABITypes() {
6248 LongWidth = LongAlign = 64;
6249 PointerWidth = PointerAlign = 64;
6250 SizeType = UnsignedLong;
6251 PtrDiffType = SignedLong;
6252 Int64Type = SignedLong;
6253 IntMaxType = Int64Type;
6254 }
6255
setN32ABITypes()6256 void setN32ABITypes() {
6257 LongWidth = LongAlign = 32;
6258 PointerWidth = PointerAlign = 32;
6259 SizeType = UnsignedInt;
6260 PtrDiffType = SignedInt;
6261 Int64Type = SignedLongLong;
6262 IntMaxType = Int64Type;
6263 }
6264
setABI(const std::string & Name)6265 bool setABI(const std::string &Name) override {
6266 if (Name == "n32") {
6267 setN32ABITypes();
6268 ABI = Name;
6269 return true;
6270 }
6271 if (Name == "n64") {
6272 setN64ABITypes();
6273 ABI = Name;
6274 return true;
6275 }
6276 return false;
6277 }
6278
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6279 void getTargetDefines(const LangOptions &Opts,
6280 MacroBuilder &Builder) const override {
6281 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6282
6283 Builder.defineMacro("__mips", "64");
6284 Builder.defineMacro("__mips64");
6285 Builder.defineMacro("__mips64__");
6286 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6287
6288 const std::string& CPUStr = getCPU();
6289 if (CPUStr == "mips64")
6290 Builder.defineMacro("__mips_isa_rev", "1");
6291 else if (CPUStr == "mips64r2")
6292 Builder.defineMacro("__mips_isa_rev", "2");
6293 else if (CPUStr == "mips64r3")
6294 Builder.defineMacro("__mips_isa_rev", "3");
6295 else if (CPUStr == "mips64r5")
6296 Builder.defineMacro("__mips_isa_rev", "5");
6297 else if (CPUStr == "mips64r6")
6298 Builder.defineMacro("__mips_isa_rev", "6");
6299
6300 if (ABI == "n32") {
6301 Builder.defineMacro("__mips_n32");
6302 Builder.defineMacro("_ABIN32", "2");
6303 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6304 }
6305 else if (ABI == "n64") {
6306 Builder.defineMacro("__mips_n64");
6307 Builder.defineMacro("_ABI64", "3");
6308 Builder.defineMacro("_MIPS_SIM", "_ABI64");
6309 }
6310 else
6311 llvm_unreachable("Invalid ABI for Mips64.");
6312 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const6313 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6314 unsigned &NumAliases) const override {
6315 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6316 { { "at" }, "$1" },
6317 { { "v0" }, "$2" },
6318 { { "v1" }, "$3" },
6319 { { "a0" }, "$4" },
6320 { { "a1" }, "$5" },
6321 { { "a2" }, "$6" },
6322 { { "a3" }, "$7" },
6323 { { "a4" }, "$8" },
6324 { { "a5" }, "$9" },
6325 { { "a6" }, "$10" },
6326 { { "a7" }, "$11" },
6327 { { "t0" }, "$12" },
6328 { { "t1" }, "$13" },
6329 { { "t2" }, "$14" },
6330 { { "t3" }, "$15" },
6331 { { "s0" }, "$16" },
6332 { { "s1" }, "$17" },
6333 { { "s2" }, "$18" },
6334 { { "s3" }, "$19" },
6335 { { "s4" }, "$20" },
6336 { { "s5" }, "$21" },
6337 { { "s6" }, "$22" },
6338 { { "s7" }, "$23" },
6339 { { "t8" }, "$24" },
6340 { { "t9" }, "$25" },
6341 { { "k0" }, "$26" },
6342 { { "k1" }, "$27" },
6343 { { "gp" }, "$28" },
6344 { { "sp","$sp" }, "$29" },
6345 { { "fp","$fp" }, "$30" },
6346 { { "ra" }, "$31" }
6347 };
6348 Aliases = GCCRegAliases;
6349 NumAliases = llvm::array_lengthof(GCCRegAliases);
6350 }
6351
hasInt128Type() const6352 bool hasInt128Type() const override { return true; }
6353 };
6354
6355 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
setDescriptionString()6356 void setDescriptionString() override {
6357 if (ABI == "n32")
6358 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6359 else
6360 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6361
6362 }
6363
6364 public:
Mips64EBTargetInfo(const llvm::Triple & Triple)6365 Mips64EBTargetInfo(const llvm::Triple &Triple)
6366 : Mips64TargetInfoBase(Triple) {}
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6367 void getTargetDefines(const LangOptions &Opts,
6368 MacroBuilder &Builder) const override {
6369 DefineStd(Builder, "MIPSEB", Opts);
6370 Builder.defineMacro("_MIPSEB");
6371 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6372 }
6373 };
6374
6375 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
setDescriptionString()6376 void setDescriptionString() override {
6377 if (ABI == "n32")
6378 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6379 else
6380 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6381 }
6382 public:
Mips64ELTargetInfo(const llvm::Triple & Triple)6383 Mips64ELTargetInfo(const llvm::Triple &Triple)
6384 : Mips64TargetInfoBase(Triple) {
6385 // Default ABI is n64.
6386 BigEndian = false;
6387 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6388 void getTargetDefines(const LangOptions &Opts,
6389 MacroBuilder &Builder) const override {
6390 DefineStd(Builder, "MIPSEL", Opts);
6391 Builder.defineMacro("_MIPSEL");
6392 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6393 }
6394 };
6395
6396 class PNaClTargetInfo : public TargetInfo {
6397 public:
PNaClTargetInfo(const llvm::Triple & Triple)6398 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6399 BigEndian = false;
6400 this->UserLabelPrefix = "";
6401 this->LongAlign = 32;
6402 this->LongWidth = 32;
6403 this->PointerAlign = 32;
6404 this->PointerWidth = 32;
6405 this->IntMaxType = TargetInfo::SignedLongLong;
6406 this->Int64Type = TargetInfo::SignedLongLong;
6407 this->DoubleAlign = 64;
6408 this->LongDoubleWidth = 64;
6409 this->LongDoubleAlign = 64;
6410 this->SizeType = TargetInfo::UnsignedInt;
6411 this->PtrDiffType = TargetInfo::SignedInt;
6412 this->IntPtrType = TargetInfo::SignedInt;
6413 this->RegParmMax = 0; // Disallow regparm
6414 }
6415
getDefaultFeatures(llvm::StringMap<bool> & Features) const6416 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6417 }
getArchDefines(const LangOptions & Opts,MacroBuilder & Builder) const6418 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6419 Builder.defineMacro("__le32__");
6420 Builder.defineMacro("__pnacl__");
6421 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6422 void getTargetDefines(const LangOptions &Opts,
6423 MacroBuilder &Builder) const override {
6424 getArchDefines(Opts, Builder);
6425 }
hasFeature(StringRef Feature) const6426 bool hasFeature(StringRef Feature) const override {
6427 return Feature == "pnacl";
6428 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const6429 void getTargetBuiltins(const Builtin::Info *&Records,
6430 unsigned &NumRecords) const override {
6431 }
getBuiltinVaListKind() const6432 BuiltinVaListKind getBuiltinVaListKind() const override {
6433 return TargetInfo::PNaClABIBuiltinVaList;
6434 }
6435 void getGCCRegNames(const char * const *&Names,
6436 unsigned &NumNames) const override;
6437 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6438 unsigned &NumAliases) const override;
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const6439 bool validateAsmConstraint(const char *&Name,
6440 TargetInfo::ConstraintInfo &Info) const override {
6441 return false;
6442 }
6443
getClobbers() const6444 const char *getClobbers() const override {
6445 return "";
6446 }
6447 };
6448
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const6449 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6450 unsigned &NumNames) const {
6451 Names = nullptr;
6452 NumNames = 0;
6453 }
6454
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const6455 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6456 unsigned &NumAliases) const {
6457 Aliases = nullptr;
6458 NumAliases = 0;
6459 }
6460
6461 class Le64TargetInfo : public TargetInfo {
6462 static const Builtin::Info BuiltinInfo[];
6463
6464 public:
Le64TargetInfo(const llvm::Triple & Triple)6465 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6466 BigEndian = false;
6467 NoAsmVariants = true;
6468 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6469 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6470 DescriptionString =
6471 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6472 }
6473
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6474 void getTargetDefines(const LangOptions &Opts,
6475 MacroBuilder &Builder) const override {
6476 DefineStd(Builder, "unix", Opts);
6477 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6478 Builder.defineMacro("__ELF__");
6479 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const6480 void getTargetBuiltins(const Builtin::Info *&Records,
6481 unsigned &NumRecords) const override {
6482 Records = BuiltinInfo;
6483 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6484 }
getBuiltinVaListKind() const6485 BuiltinVaListKind getBuiltinVaListKind() const override {
6486 return TargetInfo::PNaClABIBuiltinVaList;
6487 }
getClobbers() const6488 const char *getClobbers() const override { return ""; }
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const6489 void getGCCRegNames(const char *const *&Names,
6490 unsigned &NumNames) const override {
6491 Names = nullptr;
6492 NumNames = 0;
6493 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const6494 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6495 unsigned &NumAliases) const override {
6496 Aliases = nullptr;
6497 NumAliases = 0;
6498 }
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const6499 bool validateAsmConstraint(const char *&Name,
6500 TargetInfo::ConstraintInfo &Info) const override {
6501 return false;
6502 }
6503
hasProtectedVisibility() const6504 bool hasProtectedVisibility() const override { return false; }
6505 };
6506 } // end anonymous namespace.
6507
6508 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6509 #define BUILTIN(ID, TYPE, ATTRS) \
6510 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6511 #include "clang/Basic/BuiltinsLe64.def"
6512 };
6513
6514 namespace {
6515 static const unsigned SPIRAddrSpaceMap[] = {
6516 1, // opencl_global
6517 3, // opencl_local
6518 2, // opencl_constant
6519 4, // opencl_generic
6520 0, // cuda_device
6521 0, // cuda_constant
6522 0 // cuda_shared
6523 };
6524 class SPIRTargetInfo : public TargetInfo {
6525 public:
SPIRTargetInfo(const llvm::Triple & Triple)6526 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6527 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6528 "SPIR target must use unknown OS");
6529 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6530 "SPIR target must use unknown environment type");
6531 BigEndian = false;
6532 TLSSupported = false;
6533 LongWidth = LongAlign = 64;
6534 AddrSpaceMap = &SPIRAddrSpaceMap;
6535 UseAddrSpaceMapMangling = true;
6536 // Define available target features
6537 // These must be defined in sorted order!
6538 NoAsmVariants = true;
6539 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6540 void getTargetDefines(const LangOptions &Opts,
6541 MacroBuilder &Builder) const override {
6542 DefineStd(Builder, "SPIR", Opts);
6543 }
hasFeature(StringRef Feature) const6544 bool hasFeature(StringRef Feature) const override {
6545 return Feature == "spir";
6546 }
6547
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const6548 void getTargetBuiltins(const Builtin::Info *&Records,
6549 unsigned &NumRecords) const override {}
getClobbers() const6550 const char *getClobbers() const override {
6551 return "";
6552 }
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const6553 void getGCCRegNames(const char * const *&Names,
6554 unsigned &NumNames) const override {}
6555 bool
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & info) const6556 validateAsmConstraint(const char *&Name,
6557 TargetInfo::ConstraintInfo &info) const override {
6558 return true;
6559 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const6560 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6561 unsigned &NumAliases) const override {}
getBuiltinVaListKind() const6562 BuiltinVaListKind getBuiltinVaListKind() const override {
6563 return TargetInfo::VoidPtrBuiltinVaList;
6564 }
6565
checkCallingConvention(CallingConv CC) const6566 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6567 return (CC == CC_SpirFunction ||
6568 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
6569 }
6570
getDefaultCallingConv(CallingConvMethodType MT) const6571 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
6572 return CC_SpirFunction;
6573 }
6574 };
6575
6576
6577 class SPIR32TargetInfo : public SPIRTargetInfo {
6578 public:
SPIR32TargetInfo(const llvm::Triple & Triple)6579 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6580 PointerWidth = PointerAlign = 32;
6581 SizeType = TargetInfo::UnsignedInt;
6582 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6583 DescriptionString
6584 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6585 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6586 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6587 void getTargetDefines(const LangOptions &Opts,
6588 MacroBuilder &Builder) const override {
6589 DefineStd(Builder, "SPIR32", Opts);
6590 }
6591 };
6592
6593 class SPIR64TargetInfo : public SPIRTargetInfo {
6594 public:
SPIR64TargetInfo(const llvm::Triple & Triple)6595 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6596 PointerWidth = PointerAlign = 64;
6597 SizeType = TargetInfo::UnsignedLong;
6598 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6599 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6600 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6601 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6602 void getTargetDefines(const LangOptions &Opts,
6603 MacroBuilder &Builder) const override {
6604 DefineStd(Builder, "SPIR64", Opts);
6605 }
6606 };
6607
6608 class XCoreTargetInfo : public TargetInfo {
6609 static const Builtin::Info BuiltinInfo[];
6610 public:
XCoreTargetInfo(const llvm::Triple & Triple)6611 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6612 BigEndian = false;
6613 NoAsmVariants = true;
6614 LongLongAlign = 32;
6615 SuitableAlign = 32;
6616 DoubleAlign = LongDoubleAlign = 32;
6617 SizeType = UnsignedInt;
6618 PtrDiffType = SignedInt;
6619 IntPtrType = SignedInt;
6620 WCharType = UnsignedChar;
6621 WIntType = UnsignedInt;
6622 UseZeroLengthBitfieldAlignment = true;
6623 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6624 "-f64:32-a:0:32-n32";
6625 }
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const6626 void getTargetDefines(const LangOptions &Opts,
6627 MacroBuilder &Builder) const override {
6628 Builder.defineMacro("__XS1B__");
6629 }
getTargetBuiltins(const Builtin::Info * & Records,unsigned & NumRecords) const6630 void getTargetBuiltins(const Builtin::Info *&Records,
6631 unsigned &NumRecords) const override {
6632 Records = BuiltinInfo;
6633 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6634 }
getBuiltinVaListKind() const6635 BuiltinVaListKind getBuiltinVaListKind() const override {
6636 return TargetInfo::VoidPtrBuiltinVaList;
6637 }
getClobbers() const6638 const char *getClobbers() const override {
6639 return "";
6640 }
getGCCRegNames(const char * const * & Names,unsigned & NumNames) const6641 void getGCCRegNames(const char * const *&Names,
6642 unsigned &NumNames) const override {
6643 static const char * const GCCRegNames[] = {
6644 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6645 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
6646 };
6647 Names = GCCRegNames;
6648 NumNames = llvm::array_lengthof(GCCRegNames);
6649 }
getGCCRegAliases(const GCCRegAlias * & Aliases,unsigned & NumAliases) const6650 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6651 unsigned &NumAliases) const override {
6652 Aliases = nullptr;
6653 NumAliases = 0;
6654 }
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const6655 bool validateAsmConstraint(const char *&Name,
6656 TargetInfo::ConstraintInfo &Info) const override {
6657 return false;
6658 }
getEHDataRegisterNumber(unsigned RegNo) const6659 int getEHDataRegisterNumber(unsigned RegNo) const override {
6660 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6661 return (RegNo < 2)? RegNo : -1;
6662 }
6663 };
6664
6665 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6666 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6667 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6668 ALL_LANGUAGES },
6669 #include "clang/Basic/BuiltinsXCore.def"
6670 };
6671 } // end anonymous namespace.
6672
6673 namespace {
6674 // x86_32 Android target
6675 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
6676 public:
AndroidX86_32TargetInfo(const llvm::Triple & Triple)6677 AndroidX86_32TargetInfo(const llvm::Triple &Triple)
6678 : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
6679 SuitableAlign = 32;
6680 LongDoubleWidth = 64;
6681 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6682 }
6683 };
6684 } // end anonymous namespace
6685
6686 namespace {
6687 // x86_64 Android target
6688 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
6689 public:
AndroidX86_64TargetInfo(const llvm::Triple & Triple)6690 AndroidX86_64TargetInfo(const llvm::Triple &Triple)
6691 : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
6692 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6693 }
6694 };
6695 } // end anonymous namespace
6696
6697
6698 //===----------------------------------------------------------------------===//
6699 // Driver code
6700 //===----------------------------------------------------------------------===//
6701
AllocateTarget(const llvm::Triple & Triple)6702 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6703 llvm::Triple::OSType os = Triple.getOS();
6704
6705 switch (Triple.getArch()) {
6706 default:
6707 return nullptr;
6708
6709 case llvm::Triple::xcore:
6710 return new XCoreTargetInfo(Triple);
6711
6712 case llvm::Triple::hexagon:
6713 return new HexagonTargetInfo(Triple);
6714
6715 case llvm::Triple::aarch64:
6716 if (Triple.isOSDarwin())
6717 return new DarwinAArch64TargetInfo(Triple);
6718
6719 switch (os) {
6720 case llvm::Triple::FreeBSD:
6721 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6722 case llvm::Triple::Linux:
6723 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6724 case llvm::Triple::NetBSD:
6725 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6726 default:
6727 return new AArch64leTargetInfo(Triple);
6728 }
6729
6730 case llvm::Triple::aarch64_be:
6731 switch (os) {
6732 case llvm::Triple::FreeBSD:
6733 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6734 case llvm::Triple::Linux:
6735 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6736 case llvm::Triple::NetBSD:
6737 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6738 default:
6739 return new AArch64beTargetInfo(Triple);
6740 }
6741
6742 case llvm::Triple::arm:
6743 case llvm::Triple::thumb:
6744 if (Triple.isOSBinFormatMachO())
6745 return new DarwinARMTargetInfo(Triple);
6746
6747 switch (os) {
6748 case llvm::Triple::Linux:
6749 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6750 case llvm::Triple::FreeBSD:
6751 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6752 case llvm::Triple::NetBSD:
6753 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6754 case llvm::Triple::OpenBSD:
6755 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6756 case llvm::Triple::Bitrig:
6757 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6758 case llvm::Triple::RTEMS:
6759 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6760 case llvm::Triple::NaCl:
6761 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6762 case llvm::Triple::Win32:
6763 switch (Triple.getEnvironment()) {
6764 default:
6765 return new ARMleTargetInfo(Triple);
6766 case llvm::Triple::Itanium:
6767 return new ItaniumWindowsARMleTargetInfo(Triple);
6768 case llvm::Triple::MSVC:
6769 return new MicrosoftARMleTargetInfo(Triple);
6770 }
6771 default:
6772 return new ARMleTargetInfo(Triple);
6773 }
6774
6775 case llvm::Triple::armeb:
6776 case llvm::Triple::thumbeb:
6777 if (Triple.isOSDarwin())
6778 return new DarwinARMTargetInfo(Triple);
6779
6780 switch (os) {
6781 case llvm::Triple::Linux:
6782 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6783 case llvm::Triple::FreeBSD:
6784 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6785 case llvm::Triple::NetBSD:
6786 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6787 case llvm::Triple::OpenBSD:
6788 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6789 case llvm::Triple::Bitrig:
6790 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6791 case llvm::Triple::RTEMS:
6792 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6793 case llvm::Triple::NaCl:
6794 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6795 default:
6796 return new ARMbeTargetInfo(Triple);
6797 }
6798
6799 case llvm::Triple::msp430:
6800 return new MSP430TargetInfo(Triple);
6801
6802 case llvm::Triple::mips:
6803 switch (os) {
6804 case llvm::Triple::Linux:
6805 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6806 case llvm::Triple::RTEMS:
6807 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6808 case llvm::Triple::FreeBSD:
6809 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6810 case llvm::Triple::NetBSD:
6811 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6812 default:
6813 return new Mips32EBTargetInfo(Triple);
6814 }
6815
6816 case llvm::Triple::mipsel:
6817 switch (os) {
6818 case llvm::Triple::Linux:
6819 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6820 case llvm::Triple::RTEMS:
6821 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6822 case llvm::Triple::FreeBSD:
6823 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6824 case llvm::Triple::NetBSD:
6825 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6826 case llvm::Triple::NaCl:
6827 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6828 default:
6829 return new Mips32ELTargetInfo(Triple);
6830 }
6831
6832 case llvm::Triple::mips64:
6833 switch (os) {
6834 case llvm::Triple::Linux:
6835 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6836 case llvm::Triple::RTEMS:
6837 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6838 case llvm::Triple::FreeBSD:
6839 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6840 case llvm::Triple::NetBSD:
6841 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6842 case llvm::Triple::OpenBSD:
6843 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6844 default:
6845 return new Mips64EBTargetInfo(Triple);
6846 }
6847
6848 case llvm::Triple::mips64el:
6849 switch (os) {
6850 case llvm::Triple::Linux:
6851 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6852 case llvm::Triple::RTEMS:
6853 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6854 case llvm::Triple::FreeBSD:
6855 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6856 case llvm::Triple::NetBSD:
6857 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6858 case llvm::Triple::OpenBSD:
6859 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6860 default:
6861 return new Mips64ELTargetInfo(Triple);
6862 }
6863
6864 case llvm::Triple::le32:
6865 switch (os) {
6866 case llvm::Triple::NaCl:
6867 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6868 default:
6869 return nullptr;
6870 }
6871
6872 case llvm::Triple::le64:
6873 return new Le64TargetInfo(Triple);
6874
6875 case llvm::Triple::ppc:
6876 if (Triple.isOSDarwin())
6877 return new DarwinPPC32TargetInfo(Triple);
6878 switch (os) {
6879 case llvm::Triple::Linux:
6880 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6881 case llvm::Triple::FreeBSD:
6882 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6883 case llvm::Triple::NetBSD:
6884 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6885 case llvm::Triple::OpenBSD:
6886 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6887 case llvm::Triple::RTEMS:
6888 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6889 default:
6890 return new PPC32TargetInfo(Triple);
6891 }
6892
6893 case llvm::Triple::ppc64:
6894 if (Triple.isOSDarwin())
6895 return new DarwinPPC64TargetInfo(Triple);
6896 switch (os) {
6897 case llvm::Triple::Linux:
6898 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6899 case llvm::Triple::Lv2:
6900 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6901 case llvm::Triple::FreeBSD:
6902 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6903 case llvm::Triple::NetBSD:
6904 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6905 default:
6906 return new PPC64TargetInfo(Triple);
6907 }
6908
6909 case llvm::Triple::ppc64le:
6910 switch (os) {
6911 case llvm::Triple::Linux:
6912 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6913 case llvm::Triple::NetBSD:
6914 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6915 default:
6916 return new PPC64TargetInfo(Triple);
6917 }
6918
6919 case llvm::Triple::nvptx:
6920 return new NVPTX32TargetInfo(Triple);
6921 case llvm::Triple::nvptx64:
6922 return new NVPTX64TargetInfo(Triple);
6923
6924 case llvm::Triple::amdgcn:
6925 case llvm::Triple::r600:
6926 return new R600TargetInfo(Triple);
6927
6928 case llvm::Triple::sparc:
6929 switch (os) {
6930 case llvm::Triple::Linux:
6931 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6932 case llvm::Triple::Solaris:
6933 return new SolarisSparcV8TargetInfo(Triple);
6934 case llvm::Triple::NetBSD:
6935 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6936 case llvm::Triple::OpenBSD:
6937 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6938 case llvm::Triple::RTEMS:
6939 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6940 default:
6941 return new SparcV8TargetInfo(Triple);
6942 }
6943
6944 case llvm::Triple::sparcv9:
6945 switch (os) {
6946 case llvm::Triple::Linux:
6947 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6948 case llvm::Triple::Solaris:
6949 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6950 case llvm::Triple::NetBSD:
6951 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6952 case llvm::Triple::OpenBSD:
6953 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6954 case llvm::Triple::FreeBSD:
6955 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6956 default:
6957 return new SparcV9TargetInfo(Triple);
6958 }
6959
6960 case llvm::Triple::systemz:
6961 switch (os) {
6962 case llvm::Triple::Linux:
6963 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6964 default:
6965 return new SystemZTargetInfo(Triple);
6966 }
6967
6968 case llvm::Triple::tce:
6969 return new TCETargetInfo(Triple);
6970
6971 case llvm::Triple::x86:
6972 if (Triple.isOSDarwin())
6973 return new DarwinI386TargetInfo(Triple);
6974
6975 switch (os) {
6976 case llvm::Triple::Linux: {
6977 switch (Triple.getEnvironment()) {
6978 default:
6979 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6980 case llvm::Triple::Android:
6981 return new AndroidX86_32TargetInfo(Triple);
6982 }
6983 }
6984 case llvm::Triple::DragonFly:
6985 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6986 case llvm::Triple::NetBSD:
6987 return new NetBSDI386TargetInfo(Triple);
6988 case llvm::Triple::OpenBSD:
6989 return new OpenBSDI386TargetInfo(Triple);
6990 case llvm::Triple::Bitrig:
6991 return new BitrigI386TargetInfo(Triple);
6992 case llvm::Triple::FreeBSD:
6993 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6994 case llvm::Triple::KFreeBSD:
6995 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6996 case llvm::Triple::Minix:
6997 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6998 case llvm::Triple::Solaris:
6999 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
7000 case llvm::Triple::Win32: {
7001 switch (Triple.getEnvironment()) {
7002 default:
7003 return new X86_32TargetInfo(Triple);
7004 case llvm::Triple::Cygnus:
7005 return new CygwinX86_32TargetInfo(Triple);
7006 case llvm::Triple::GNU:
7007 return new MinGWX86_32TargetInfo(Triple);
7008 case llvm::Triple::Itanium:
7009 case llvm::Triple::MSVC:
7010 return new MicrosoftX86_32TargetInfo(Triple);
7011 }
7012 }
7013 case llvm::Triple::Haiku:
7014 return new HaikuX86_32TargetInfo(Triple);
7015 case llvm::Triple::RTEMS:
7016 return new RTEMSX86_32TargetInfo(Triple);
7017 case llvm::Triple::NaCl:
7018 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
7019 default:
7020 return new X86_32TargetInfo(Triple);
7021 }
7022
7023 case llvm::Triple::x86_64:
7024 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
7025 return new DarwinX86_64TargetInfo(Triple);
7026
7027 switch (os) {
7028 case llvm::Triple::CloudABI:
7029 return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
7030 case llvm::Triple::Linux: {
7031 switch (Triple.getEnvironment()) {
7032 default:
7033 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
7034 case llvm::Triple::Android:
7035 return new AndroidX86_64TargetInfo(Triple);
7036 }
7037 }
7038 case llvm::Triple::DragonFly:
7039 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
7040 case llvm::Triple::NetBSD:
7041 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
7042 case llvm::Triple::OpenBSD:
7043 return new OpenBSDX86_64TargetInfo(Triple);
7044 case llvm::Triple::Bitrig:
7045 return new BitrigX86_64TargetInfo(Triple);
7046 case llvm::Triple::FreeBSD:
7047 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7048 case llvm::Triple::KFreeBSD:
7049 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7050 case llvm::Triple::Solaris:
7051 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
7052 case llvm::Triple::Win32: {
7053 switch (Triple.getEnvironment()) {
7054 default:
7055 return new X86_64TargetInfo(Triple);
7056 case llvm::Triple::GNU:
7057 return new MinGWX86_64TargetInfo(Triple);
7058 case llvm::Triple::MSVC:
7059 return new MicrosoftX86_64TargetInfo(Triple);
7060 }
7061 }
7062 case llvm::Triple::NaCl:
7063 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
7064 case llvm::Triple::PS4:
7065 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
7066 default:
7067 return new X86_64TargetInfo(Triple);
7068 }
7069
7070 case llvm::Triple::spir: {
7071 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7072 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7073 return nullptr;
7074 return new SPIR32TargetInfo(Triple);
7075 }
7076 case llvm::Triple::spir64: {
7077 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7078 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7079 return nullptr;
7080 return new SPIR64TargetInfo(Triple);
7081 }
7082 }
7083 }
7084
7085 /// CreateTargetInfo - Return the target info object for the specified target
7086 /// triple.
7087 TargetInfo *
CreateTargetInfo(DiagnosticsEngine & Diags,const std::shared_ptr<TargetOptions> & Opts)7088 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
7089 const std::shared_ptr<TargetOptions> &Opts) {
7090 llvm::Triple Triple(Opts->Triple);
7091
7092 // Construct the target
7093 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
7094 if (!Target) {
7095 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
7096 return nullptr;
7097 }
7098 Target->TargetOpts = Opts;
7099
7100 // Set the target CPU if specified.
7101 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
7102 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
7103 return nullptr;
7104 }
7105
7106 // Set the target ABI if specified.
7107 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
7108 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
7109 return nullptr;
7110 }
7111
7112 // Set the fp math unit.
7113 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
7114 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
7115 return nullptr;
7116 }
7117
7118 // Compute the default target features, we need the target to handle this
7119 // because features may have dependencies on one another.
7120 llvm::StringMap<bool> Features;
7121 Target->getDefaultFeatures(Features);
7122
7123 // Apply the user specified deltas.
7124 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
7125 I < N; ++I) {
7126 const char *Name = Opts->FeaturesAsWritten[I].c_str();
7127 // Apply the feature via the target.
7128 bool Enabled = Name[0] == '+';
7129 Target->setFeatureEnabled(Features, Name + 1, Enabled);
7130 }
7131
7132 // Add the features to the compile options.
7133 //
7134 // FIXME: If we are completely confident that we have the right set, we only
7135 // need to pass the minuses.
7136 Opts->Features.clear();
7137 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
7138 ie = Features.end(); it != ie; ++it)
7139 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
7140 if (!Target->handleTargetFeatures(Opts->Features, Diags))
7141 return nullptr;
7142
7143 return Target.release();
7144 }
7145