1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20 /*****************************************************************************/
21 /* */
22 /* File Name : decoder_api_main.c */
23 /* */
24 /* Description : Functions which recieve the API call from user */
25 /* */
26 /* List of Functions : <List the functions defined in this file> */
27 /* */
28 /* Issues / Problems : None */
29 /* */
30 /* Revision History : */
31 /* */
32 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
33 /* 30 05 2007 Rajneesh Creation */
34 /* */
35 /*****************************************************************************/
36
37 /*****************************************************************************/
38 /* File Includes */
39 /*****************************************************************************/
40
41 /* System include files */
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <stddef.h>
45 #include <string.h>
46
47 /* User include files */
48 #include "iv_datatypedef.h"
49 #include "iv.h"
50 #include "ivd.h"
51 #include "ithread.h"
52
53 #include "impeg2_job_queue.h"
54 #include "impeg2_macros.h"
55 #include "impeg2_buf_mgr.h"
56 #include "impeg2_disp_mgr.h"
57 #include "impeg2_defs.h"
58 #include "impeg2_platform_macros.h"
59 #include "impeg2_inter_pred.h"
60 #include "impeg2_idct.h"
61 #include "impeg2_format_conv.h"
62 #include "impeg2_mem_func.h"
63
64 #include "impeg2d.h"
65 #include "impeg2d_api.h"
66 #include "impeg2d_bitstream.h"
67 #include "impeg2d_debug.h"
68 #include "impeg2d_structs.h"
69 #include "impeg2d_mc.h"
70 #include "impeg2d_pic_proc.h"
71
72 #define NUM_FRAMES_LIMIT_ENABLED 0
73
74 #ifdef LOGO_EN
75 #include "impeg2_ittiam_logo.h"
76 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht) impeg2_insert_logo(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht);
77 #else
78 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht)
79 #endif
80
81 #if NUM_FRAMES_LIMIT_ENABLED
82 #define NUM_FRAMES_LIMIT 10000
83 #else
84 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
85 #endif
86
87 #define CODEC_NAME "MPEG2VDEC"
88 #define CODEC_RELEASE_TYPE "eval"
89 #define CODEC_RELEASE_VER "01.00"
90 #define CODEC_VENDOR "ITTIAM"
91
92 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
93 strcpy(version_string,"@(#)Id:"); \
94 strcat(version_string,codec_name); \
95 strcat(version_string,"_"); \
96 strcat(version_string,codec_release_type); \
97 strcat(version_string," Ver:"); \
98 strcat(version_string,codec_release_ver); \
99 strcat(version_string," Released by "); \
100 strcat(version_string,codec_vendor); \
101 strcat(version_string," Build: "); \
102 strcat(version_string,__DATE__); \
103 strcat(version_string," @ "); \
104 strcat(version_string,__TIME__);
105
106
107 #define MIN_OUT_BUFS_420 3
108 #define MIN_OUT_BUFS_422ILE 1
109 #define MIN_OUT_BUFS_RGB565 1
110 #define MIN_OUT_BUFS_420SP 2
111
112
113 void impeg2d_init_arch(void *pv_codec);
114 void impeg2d_init_function_ptr(void *pv_codec);
115
116 /*****************************************************************************/
117 /* */
118 /* Function Name : impeg2d_api_rel_display_frame */
119 /* */
120 /* Description : Release displ buffers that will be shared between decoder */
121 /* and application */
122 /* Inputs : Error message */
123 /* Globals : None */
124 /* Processing : Just prints error message to console */
125 /* Outputs : Error mesage to the console */
126 /* Returns : None */
127 /* */
128 /* Issues : <List any issues or problems with this function> */
129 /* */
130 /* Revision History: */
131 /* */
132 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
133 /* 27 05 2006 Sankar Creation */
134 /* */
135 /*****************************************************************************/
impeg2d_api_rel_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)136 IV_API_CALL_STATUS_T impeg2d_api_rel_display_frame(iv_obj_t *ps_dechdl,
137 void *pv_api_ip,
138 void *pv_api_op)
139 {
140
141 ivd_rel_display_frame_ip_t *dec_rel_disp_ip;
142 ivd_rel_display_frame_op_t *dec_rel_disp_op;
143
144 dec_state_t *ps_dec_state;
145 dec_state_multi_core_t *ps_dec_state_multi_core;
146
147
148 dec_rel_disp_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
149 dec_rel_disp_op = (ivd_rel_display_frame_op_t *)pv_api_op;
150
151 dec_rel_disp_op->u4_error_code = 0;
152 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
153 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
154
155
156 /* If not in shared disp buf mode, return */
157 if(0 == ps_dec_state->u4_share_disp_buf)
158 return IV_SUCCESS;
159
160 if(NULL == ps_dec_state->pv_pic_buf_mg)
161 return IV_SUCCESS;
162
163
164 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, dec_rel_disp_ip->u4_disp_buf_id, BUF_MGR_DISP);
165
166 return IV_SUCCESS;
167 }
168
169 /*****************************************************************************/
170 /* */
171 /* Function Name : impeg2d_api_set_display_frame */
172 /* */
173 /* Description : Sets display buffers that will be shared between decoder */
174 /* and application */
175 /* Inputs : Error message */
176 /* Globals : None */
177 /* Processing : Just prints error message to console */
178 /* Outputs : Error mesage to the console */
179 /* Returns : None */
180 /* */
181 /* Issues : <List any issues or problems with this function> */
182 /* */
183 /* Revision History: */
184 /* */
185 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
186 /* 27 05 2006 Sankar Creation */
187 /* */
188 /*****************************************************************************/
impeg2d_api_set_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)189 IV_API_CALL_STATUS_T impeg2d_api_set_display_frame(iv_obj_t *ps_dechdl,
190 void *pv_api_ip,
191 void *pv_api_op)
192 {
193
194 ivd_set_display_frame_ip_t *dec_disp_ip;
195 ivd_set_display_frame_op_t *dec_disp_op;
196
197 UWORD32 i;
198 dec_state_t *ps_dec_state;
199 dec_state_multi_core_t *ps_dec_state_multi_core;
200 UWORD32 u4_num_disp_bufs;
201
202
203 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
204 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
205 dec_disp_op->u4_error_code = 0;
206
207 u4_num_disp_bufs = dec_disp_ip->num_disp_bufs;
208 if(u4_num_disp_bufs > BUF_MGR_MAX_CNT)
209 u4_num_disp_bufs = BUF_MGR_MAX_CNT;
210
211 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
212 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
213
214 if(ps_dec_state->u4_share_disp_buf)
215 {
216 pic_buf_t *ps_pic_buf;
217 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
218 for(i = 0; i < u4_num_disp_bufs; i++)
219 {
220
221 ps_pic_buf->pu1_y = dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
222 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
223 {
224 ps_pic_buf->pu1_u = dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
225 ps_pic_buf->pu1_v = dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
226 }
227 else
228 {
229 ps_pic_buf->pu1_u = ps_dec_state->pu1_chroma_ref_buf[i];
230 ps_pic_buf->pu1_v = ps_dec_state->pu1_chroma_ref_buf[i] +
231 ((ps_dec_state->u2_create_max_width * ps_dec_state->u2_create_max_height) >> 2);
232 }
233
234 ps_pic_buf->i4_buf_id = i;
235
236 ps_pic_buf->u1_used_as_ref = 0;
237
238 ps_pic_buf->u4_ts = 0;
239
240 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
241 impeg2_buf_mgr_set_status(ps_dec_state->pv_pic_buf_mg, i, BUF_MGR_DISP);
242 ps_pic_buf++;
243
244 }
245 }
246 memcpy(&(ps_dec_state->as_disp_buffers[0]),
247 &(dec_disp_ip->s_disp_buffer),
248 u4_num_disp_bufs * sizeof(ivd_out_bufdesc_t));
249
250 return IV_SUCCESS;
251
252 }
253
impeg2d_api_set_num_cores(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)254 IV_API_CALL_STATUS_T impeg2d_api_set_num_cores(iv_obj_t *ps_dechdl,
255 void *pv_api_ip,
256 void *pv_api_op)
257 {
258 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
259 impeg2d_ctl_set_num_cores_op_t *ps_op;
260 dec_state_t *ps_dec_state;
261 dec_state_multi_core_t *ps_dec_state_multi_core;
262
263 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
264 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
265
266 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
267 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
268
269 if(ps_ip->u4_num_cores > 0)
270 {
271
272
273 WORD32 i;
274 for(i = 0; i < MAX_THREADS; i++)
275 ps_dec_state_multi_core->ps_dec_state[i]->i4_num_cores = ps_ip->u4_num_cores;
276 }
277 else
278 {
279 ps_dec_state->i4_num_cores = 1;
280 }
281 ps_op->u4_error_code = IV_SUCCESS;
282
283 return IV_SUCCESS;
284 }
285
286 /**
287 *******************************************************************************
288 *
289 * @brief
290 * Sets Processor type
291 *
292 * @par Description:
293 * Sets Processor type
294 *
295 * @param[in] ps_codec_obj
296 * Pointer to codec object at API level
297 *
298 * @param[in] pv_api_ip
299 * Pointer to input argument structure
300 *
301 * @param[out] pv_api_op
302 * Pointer to output argument structure
303 *
304 * @returns Status
305 *
306 * @remarks
307 *
308 *
309 *******************************************************************************
310 */
311
impeg2d_set_processor(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)312 IV_API_CALL_STATUS_T impeg2d_set_processor(iv_obj_t *ps_codec_obj,
313 void *pv_api_ip,
314 void *pv_api_op)
315 {
316 impeg2d_ctl_set_processor_ip_t *ps_ip;
317 impeg2d_ctl_set_processor_op_t *ps_op;
318 dec_state_t *ps_codec;
319 dec_state_multi_core_t *ps_dec_state_multi_core;
320
321 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
322 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
323
324 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
325 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
326
327 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
328 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
329
330 impeg2d_init_function_ptr(ps_codec);
331
332
333 ps_op->u4_error_code = 0;
334 return IV_SUCCESS;
335 }
336 /*****************************************************************************/
337 /* */
338 /* Function Name : impeg2d_fill_mem_rec */
339 /* */
340 /* Description : */
341 /* Inputs : */
342 /* Globals : */
343 /* Processing : */
344 /* Outputs : */
345 /* Returns : */
346 /* */
347 /* Issues : */
348 /* */
349 /* Revision History: */
350 /* */
351 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
352 /* 17 09 2007 Rajendra C Y Draft */
353 /* */
354 /*****************************************************************************/
impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t * ps_ip,impeg2d_fill_mem_rec_op_t * ps_op)355 void impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t *ps_ip,
356 impeg2d_fill_mem_rec_op_t *ps_op)
357 {
358 UWORD32 u4_i;
359
360 UWORD8 u1_no_rec = 0;
361 UWORD32 max_frm_width,max_frm_height,max_frm_size;
362 iv_mem_rec_t *ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
363 WORD32 i4_num_threads;
364 WORD32 i4_share_disp_buf, i4_chroma_format;
365 WORD32 i4_chroma_size;
366
367 max_frm_width = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd);
368 max_frm_height = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht);
369
370 max_frm_size = (max_frm_width * max_frm_height * 3) >> 1;/* 420 P */
371
372 i4_chroma_size = max_frm_width * max_frm_height / 4;
373
374 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_share_disp_buf))
375 {
376 #ifndef LOGO_EN
377 i4_share_disp_buf = ps_ip->u4_share_disp_buf;
378 #else
379 i4_share_disp_buf = 0;
380 #endif
381 }
382 else
383 {
384 i4_share_disp_buf = 0;
385 }
386 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, e_output_format))
387 {
388 i4_chroma_format = ps_ip->e_output_format;
389 }
390 else
391 {
392 i4_chroma_format = -1;
393 }
394
395
396 if( (i4_chroma_format != IV_YUV_420P) &&
397 (i4_chroma_format != IV_YUV_420SP_UV) &&
398 (i4_chroma_format != IV_YUV_420SP_VU))
399 {
400 i4_share_disp_buf = 0;
401 }
402
403 /*************************************************************************/
404 /* Fill the memory requirement XDM Handle */
405 /*************************************************************************/
406 /* ! */
407 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
408 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
409 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
410
411 ps_mem_rec++;
412 u1_no_rec++;
413
414 {
415 /*************************************************************************/
416 /* Fill the memory requirement for threads context */
417 /*************************************************************************/
418 /* ! */
419 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
420 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
421 ps_mem_rec->u4_mem_size = sizeof(dec_state_multi_core_t);
422
423 ps_mem_rec++;
424 u1_no_rec++;
425 }
426
427 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
428 {
429 /*************************************************************************/
430 /* Fill the memory requirement for MPEG2 Decoder Context */
431 /*************************************************************************/
432 /* ! */
433 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
434 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
435 ps_mem_rec->u4_mem_size = sizeof(dec_state_t);
436
437 ps_mem_rec++;
438 u1_no_rec++;
439
440 /* To store thread handle */
441 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
442 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
443 ps_mem_rec->u4_mem_size = ithread_get_handle_size();
444
445 ps_mem_rec++;
446 u1_no_rec++;
447
448 /*************************************************************************/
449 /* Fill the memory requirement for Motion Compensation Buffers */
450 /*************************************************************************/
451 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
452 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_SCRATCH_MEM;
453
454 /* for mc_fw_buf.pu1_y */
455 ps_mem_rec->u4_mem_size = MB_LUMA_MEM_SIZE;
456
457 /* for mc_fw_buf.pu1_u */
458 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
459
460 /* for mc_fw_buf.pu1_v */
461 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
462
463 /* for mc_bk_buf.pu1_y */
464 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
465
466 /* for mc_bk_buf.pu1_u */
467 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
468
469 /* for mc_bk_buf.pu1_v */
470 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
471
472 /* for mc_buf.pu1_y */
473 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
474
475 /* for mc_buf.pu1_u */
476 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
477
478 /* for mc_buf.pu1_v */
479 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
480
481 ps_mem_rec++;
482 u1_no_rec++;
483
484
485 /*************************************************************************/
486 /* Fill the memory requirement Stack Context */
487 /*************************************************************************/
488 /* ! */
489 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
490 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
491 ps_mem_rec->u4_mem_size = 392;
492
493 ps_mem_rec++;
494 u1_no_rec++;
495 }
496
497
498
499 {
500 /*************************************************************************/
501 /* Fill the memory requirement for Picture Buffer Manager */
502 /*************************************************************************/
503 /* ! */
504 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
505 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
506 ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t) + sizeof(pic_buf_t) * BUF_MGR_MAX_CNT;
507
508 ps_mem_rec++;
509 u1_no_rec++;
510 }
511 /*************************************************************************/
512 /* Internal Frame Buffers */
513 /*************************************************************************/
514 /* ! */
515
516 {
517 for(u4_i = 0; u4_i < NUM_INT_FRAME_BUFFERS; u4_i++)
518 {
519 /* ! */
520 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
521 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
522 if(0 == i4_share_disp_buf)
523 ps_mem_rec->u4_mem_size = max_frm_size;
524 else if(IV_YUV_420P != i4_chroma_format)
525 {
526 /* If color format is not 420P and it is shared, then allocate for chroma */
527 ps_mem_rec->u4_mem_size = i4_chroma_size * 2;
528 }
529 else
530 ps_mem_rec->u4_mem_size = 64;
531 ps_mem_rec++;
532 u1_no_rec++;
533 }
534 }
535
536
537
538 {
539 WORD32 i4_job_queue_size;
540 WORD32 i4_num_jobs;
541
542 /* One job per row of MBs */
543 i4_num_jobs = max_frm_height >> 4;
544
545 /* One format convert/frame copy job per row of MBs for non-shared mode*/
546 i4_num_jobs += max_frm_height >> 4;
547
548
549 i4_job_queue_size = impeg2_jobq_ctxt_size();
550 i4_job_queue_size += i4_num_jobs * sizeof(job_t);
551 ps_mem_rec->u4_mem_size = i4_job_queue_size;
552 ps_mem_rec->u4_mem_alignment = 128;
553 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
554
555 ps_mem_rec++;
556 u1_no_rec++;
557
558 }
559
560 ps_mem_rec->u4_mem_alignment = 128;
561 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
562 ps_mem_rec->u4_mem_size = sizeof(iv_mem_rec_t) * (NUM_MEM_RECORDS);
563 ps_mem_rec++;
564 u1_no_rec++;
565 ps_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = u1_no_rec;
566 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
567 }
568
569
570 /*****************************************************************************/
571 /* */
572 /* Function Name : impeg2d_api_get_version */
573 /* */
574 /* Description : */
575 /* */
576 /* Inputs : */
577 /* Globals : <Does it use any global variables?> */
578 /* Outputs : */
579 /* Returns : void */
580 /* */
581 /* Issues : none */
582 /* */
583 /* Revision History: */
584 /* */
585 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
586 /* 22 10 2008 100356 Draft */
587 /* */
588 /*****************************************************************************/
impeg2d_api_get_version(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)589 IV_API_CALL_STATUS_T impeg2d_api_get_version(iv_obj_t *ps_dechdl,
590 void *pv_api_ip,
591 void *pv_api_op)
592 {
593 char au1_version_string[512];
594
595 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
596 impeg2d_ctl_getversioninfo_op_t *ps_op;
597
598 UNUSED(ps_dechdl);
599
600 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
601 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
602
603 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
604
605 VERSION(au1_version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
606 CODEC_VENDOR);
607
608 if((WORD32)ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size <= 0)
609 {
610 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
611 return (IV_FAIL);
612 }
613
614 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size
615 >= (strlen(au1_version_string) + 1))
616 {
617 memcpy(ps_ip->s_ivd_ctl_getversioninfo_ip_t.pv_version_buffer,
618 au1_version_string, (strlen(au1_version_string) + 1));
619 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
620 }
621 else
622 {
623 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
624 }
625
626 return (IV_SUCCESS);
627 }
628
629 /*****************************************************************************/
630 /* */
631 /* Function Name : impeg2d_api_get_buf_info */
632 /* */
633 /* Description : */
634 /* */
635 /* Inputs : */
636 /* Globals : <Does it use any global variables?> */
637 /* Outputs : */
638 /* Returns : void */
639 /* */
640 /* Issues : none */
641 /* */
642 /* Revision History: */
643 /* */
644 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
645 /* 22 10 2008 100356 Draft */
646 /* */
647 /*****************************************************************************/
impeg2d_api_get_buf_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)648 IV_API_CALL_STATUS_T impeg2d_api_get_buf_info(iv_obj_t *ps_dechdl,
649 void *pv_api_ip,
650 void *pv_api_op)
651 {
652 dec_state_t *ps_dec_state;
653 dec_state_multi_core_t *ps_dec_state_multi_core;
654 impeg2d_ctl_getbufinfo_ip_t *ps_ctl_bufinfo_ip =
655 (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
656 impeg2d_ctl_getbufinfo_op_t *ps_ctl_bufinfo_op =
657 (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
658 UWORD32 u4_i, u4_stride, u4_height;
659 UNUSED(ps_ctl_bufinfo_ip);
660
661 ps_dec_state_multi_core =
662 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
663 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
664
665 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs = 1;
666 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 1;
667
668 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
669 {
670 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
671 MIN_OUT_BUFS_420;
672 }
673 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV)
674 || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
675 {
676 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
677 MIN_OUT_BUFS_420SP;
678 }
679 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
680 {
681 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
682 MIN_OUT_BUFS_422ILE;
683 }
684 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565)
685 {
686 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
687 MIN_OUT_BUFS_RGB565;
688 }
689 else
690 {
691 //Invalid chroma format; Error code may be updated, verify in testing if needed
692 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code =
693 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
694 return IV_FAIL;
695 }
696
697 for(u4_i = 0; u4_i < IVD_VIDDEC_MAX_IO_BUFFERS; u4_i++)
698 {
699 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
700 0;
701 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[u4_i] =
702 0;
703 }
704
705 for(u4_i = 0;
706 u4_i < ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs;
707 u4_i++)
708 {
709 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
710 MAX_BITSTREAM_BUFFER_SIZE;
711 }
712
713 if (0 == ps_dec_state->u4_frm_buf_stride)
714 {
715 if (1 == ps_dec_state->u2_header_done)
716 {
717 u4_stride = ps_dec_state->u2_horizontal_size;
718 }
719 else
720 {
721 u4_stride = ps_dec_state->u2_create_max_width;
722 }
723 }
724 else
725 {
726 u4_stride = ps_dec_state->u4_frm_buf_stride;
727 }
728 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4;
729
730 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
731 {
732 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] =
733 (u4_stride * u4_height);
734 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] =
735 (u4_stride * u4_height) >> 2;
736 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] =
737 (u4_stride * u4_height) >> 2;
738 }
739 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV)
740 || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
741 {
742 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] =
743 (u4_stride * u4_height);
744 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] =
745 (u4_stride * u4_height) >> 1;
746 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] = 0;
747 }
748 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
749 {
750 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] =
751 (u4_stride * u4_height) * 2;
752 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] =
753 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] =
754 0;
755 }
756
757 /* Adding initialization for 2 uninitialized values */
758 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs = 1;
759 if(ps_dec_state->u4_share_disp_buf)
760 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs =
761 NUM_INT_FRAME_BUFFERS;
762 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_size = MAX_FRM_SIZE;
763
764 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = IV_SUCCESS;
765
766 return (IV_SUCCESS);
767 }
768
769 /*****************************************************************************/
770 /* */
771 /* Function Name : impeg2d_api_set_flush_mode */
772 /* */
773 /* Description : */
774 /* */
775 /* Inputs : */
776 /* Globals : <Does it use any global variables?> */
777 /* Outputs : */
778 /* Returns : void */
779 /* */
780 /* Issues : none */
781 /* */
782 /* Revision History: */
783 /* */
784 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
785 /* 08 06 2009 100356 RAVI */
786 /* */
787 /*****************************************************************************/
impeg2d_api_set_flush_mode(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)788 IV_API_CALL_STATUS_T impeg2d_api_set_flush_mode(iv_obj_t *ps_dechdl,
789 void *pv_api_ip,
790 void *pv_api_op)
791 {
792 dec_state_t *ps_dec_state;
793 dec_state_multi_core_t *ps_dec_state_multi_core;
794 impeg2d_ctl_flush_op_t *ps_ctl_dec_op =
795 (impeg2d_ctl_flush_op_t*)pv_api_op;
796
797 UNUSED(pv_api_ip);
798
799 ps_dec_state_multi_core =
800 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
801 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
802
803 ps_dec_state->u1_flushfrm = 1;
804
805 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_size =
806 sizeof(impeg2d_ctl_flush_op_t);
807 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_error_code = IV_SUCCESS;
808
809 return (IV_SUCCESS);
810 }
811
812 /*****************************************************************************/
813 /* */
814 /* Function Name : impeg2d_api_set_default */
815 /* */
816 /* Description : */
817 /* */
818 /* Inputs : */
819 /* Globals : <Does it use any global variables?> */
820 /* Outputs : */
821 /* Returns : void */
822 /* */
823 /* Issues : none */
824 /* */
825 /* Revision History: */
826 /* */
827 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
828 /* 08 06 2009 100356 RAVI */
829 /* */
830 /*****************************************************************************/
impeg2d_api_set_default(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)831 IV_API_CALL_STATUS_T impeg2d_api_set_default(iv_obj_t *ps_dechdl,
832 void *pv_api_ip,
833 void *pv_api_op)
834 {
835 dec_state_t *ps_dec_state;
836 dec_state_multi_core_t *ps_dec_state_multi_core;
837 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op =
838 (impeg2d_ctl_set_config_op_t *)pv_api_op;
839
840 UNUSED(pv_api_ip);
841
842 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
843 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_size =
844 sizeof(impeg2d_ctl_set_config_op_t);
845
846 ps_dec_state_multi_core =
847 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
848 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
849
850 ps_dec_state->u1_flushfrm = 0;
851 ps_dec_state->u2_decode_header = 1;
852
853 if (1 == ps_dec_state->u2_header_done)
854 {
855 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
856 }
857
858 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
859
860 return (IV_SUCCESS);
861
862 }
863
864 /*****************************************************************************/
865 /* */
866 /* Function Name : impeg2d_api_reset */
867 /* */
868 /* Description : */
869 /* */
870 /* Inputs : */
871 /* Globals : <Does it use any global variables?> */
872 /* Outputs : */
873 /* Returns : void */
874 /* */
875 /* Issues : none */
876 /* */
877 /* Revision History: */
878 /* */
879 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
880 /* 08 06 2009 100356 RAVI */
881 /* */
882 /*****************************************************************************/
impeg2d_api_reset(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)883 IV_API_CALL_STATUS_T impeg2d_api_reset(iv_obj_t *ps_dechdl,
884 void *pv_api_ip,
885 void *pv_api_op)
886 {
887 dec_state_t *ps_dec_state;
888 dec_state_multi_core_t *ps_dec_state_multi_core;
889 UNUSED(pv_api_ip);
890 impeg2d_ctl_reset_op_t *s_ctl_reset_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
891
892 WORD32 i4_num_threads;
893
894 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
895 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
896
897 if(ps_dec_state_multi_core != NULL)
898 {
899 if(ps_dec_state->aps_ref_pics[1] != NULL)
900 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF);
901 if(ps_dec_state->aps_ref_pics[0] != NULL)
902 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
903 while(1)
904 {
905 pic_buf_t *ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id);
906 if(NULL == ps_disp_pic)
907 break;
908 if(0 == ps_dec_state->u4_share_disp_buf)
909 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
910
911 }
912
913 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
914 {
915
916 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
917
918
919 /* --------------------------------------------------------------------- */
920 /* Initializations */
921
922 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
923 ps_dec_state->u4_frm_buf_stride = 0;
924 ps_dec_state->u2_is_mpeg2 = 0;
925 ps_dec_state->aps_ref_pics[0] = NULL;
926 ps_dec_state->aps_ref_pics[1] = NULL;
927 }
928 }
929 else
930 {
931 s_ctl_reset_op->s_ivd_ctl_reset_op_t.u4_error_code =
932 IMPEG2D_INIT_NOT_DONE;
933 }
934
935 return(IV_SUCCESS);
936 }
937
938 /*****************************************************************************/
939 /* */
940 /* Function Name : impeg2d_api_set_params */
941 /* */
942 /* Description : */
943 /* */
944 /* Inputs : */
945 /* Globals : <Does it use any global variables?> */
946 /* Outputs : */
947 /* Returns : void */
948 /* */
949 /* Issues : none */
950 /* */
951 /* Revision History: */
952 /* */
953 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
954 /* 08 06 2009 100356 RAVI */
955 /* */
956 /*****************************************************************************/
impeg2d_api_set_params(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)957 IV_API_CALL_STATUS_T impeg2d_api_set_params(iv_obj_t *ps_dechdl,void *pv_api_ip,void *pv_api_op)
958 {
959 dec_state_t *ps_dec_state;
960 dec_state_multi_core_t *ps_dec_state_multi_core;
961 impeg2d_ctl_set_config_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
962 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
963
964 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
965 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
966
967 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_HEADER) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_FRAME))
968 {
969 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
970 return(IV_FAIL);
971 }
972
973 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DISPLAY_FRAME_OUT) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DECODE_FRAME_OUT))
974 {
975 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
976 return(IV_FAIL);
977 }
978
979 if( (WORD32) ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_skip_mode < IVD_SKIP_NONE)
980 {
981 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
982 return(IV_FAIL);
983 }
984
985 if(ps_dec_state->u2_header_done == 1)
986 {
987 if(((WORD32)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < 0) ||
988 ((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < ps_dec_state->u2_frame_width)))
989 {
990 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
991 return(IV_FAIL);
992 }
993
994 }
995 else
996 {
997 if(((WORD32)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < 0) ||
998 ((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < ps_dec_state->u2_horizontal_size)))
999 {
1000 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1001 return(IV_FAIL);
1002 }
1003 }
1004
1005
1006 ps_dec_state->u2_decode_header = (UWORD8)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode;
1007
1008 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0)
1009 {
1010 if(ps_dec_state->u2_header_done == 1)
1011 {
1012 if (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd > ps_dec_state->u2_frame_width)
1013 {
1014 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd;
1015 }
1016 }
1017 else
1018 {
1019 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd;
1020 }
1021
1022 }
1023 else
1024 {
1025
1026 if(ps_dec_state->u2_header_done == 1)
1027 {
1028 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
1029 }
1030 else
1031 {
1032 ps_dec_state->u4_frm_buf_stride = 0;
1033 }
1034 }
1035
1036
1037 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode == IVD_DECODE_FRAME)
1038 {
1039 ps_dec_state->u1_flushfrm = 0;
1040 }
1041
1042
1043 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
1044 return(IV_SUCCESS);
1045
1046 }
1047
1048 /*****************************************************************************/
1049 /* */
1050 /* Function Name : impeg2d_api_get_status */
1051 /* */
1052 /* Description : */
1053 /* */
1054 /* Inputs : */
1055 /* Globals : <Does it use any global variables?> */
1056 /* Outputs : */
1057 /* Returns : void */
1058 /* */
1059 /* Issues : none */
1060 /* */
1061 /* Revision History: */
1062 /* */
1063 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1064 /* 08 06 2009 100356 RAVI */
1065 /* */
1066 /*****************************************************************************/
impeg2d_api_get_status(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1067 IV_API_CALL_STATUS_T impeg2d_api_get_status(iv_obj_t *ps_dechdl,
1068 void *pv_api_ip,
1069 void *pv_api_op)
1070 {
1071 dec_state_t *ps_dec_state;
1072 dec_state_multi_core_t *ps_dec_state_multi_core;
1073 UWORD32 u4_i,u4_stride,u4_height;
1074 impeg2d_ctl_getstatus_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
1075 impeg2d_ctl_getstatus_op_t *ps_ctl_dec_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
1076 UNUSED(ps_ctl_dec_ip);
1077
1078 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1079 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1080
1081 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_size = sizeof(impeg2d_ctl_getstatus_op_t);
1082 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_num_disp_bufs = 1;
1083 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_ht = ps_dec_state->u2_frame_height;
1084 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_wd = ps_dec_state->u2_frame_width;
1085 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_frame_rate = ps_dec_state->u2_framePeriod;
1086
1087
1088 if(ps_dec_state->u2_progressive_sequence == 1)
1089 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_PROGRESSIVE ;
1090 else
1091 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_INTERLACED;
1092
1093
1094 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_output_chroma_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
1095 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs = 1;
1096 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = 1;
1097
1098
1099 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1100 {
1101 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1102 }
1103 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1104 {
1105 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1106 }
1107 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565)
1108 {
1109 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1110 }
1111 else
1112 {
1113 //Invalid chroma format; Error code may be updated, verify in testing if needed
1114 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
1115 return IV_FAIL;
1116 }
1117
1118 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1119 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1120
1121 for(u4_i = 0; u4_i < ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs; u4_i++)
1122 {
1123 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[u4_i] = MAX_BITSTREAM_BUFFER_SIZE;
1124 }
1125
1126 u4_stride = ps_dec_state->u4_frm_buf_stride;
1127 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4;
1128
1129 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1130 {
1131 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1132 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>2 ;
1133 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = (u4_stride * u4_height)>>2;
1134 }
1135 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV) || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
1136 {
1137 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1138 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>1 ;
1139 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1140 }
1141 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1142 {
1143 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height)*2;
1144 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1145 }
1146
1147 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IV_SUCCESS;
1148
1149 return(IV_SUCCESS);
1150
1151 }
1152
1153 /**
1154 *******************************************************************************
1155 *
1156 * @brief
1157 * Gets frame dimensions/offsets
1158 *
1159 * @par Description:
1160 * Gets frame buffer chararacteristics such a x & y offsets display and
1161 * buffer dimensions
1162 *
1163 * @param[in] ps_codec_obj
1164 * Pointer to codec object at API level
1165 *
1166 * @param[in] pv_api_ip
1167 * Pointer to input argument structure
1168 *
1169 * @param[out] pv_api_op
1170 * Pointer to output argument structure
1171 *
1172 * @returns Status
1173 *
1174 * @remarks
1175 *
1176 *
1177 *******************************************************************************
1178 */
impeg2d_get_frame_dimensions(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)1179 IV_API_CALL_STATUS_T impeg2d_get_frame_dimensions(iv_obj_t *ps_codec_obj,
1180 void *pv_api_ip,
1181 void *pv_api_op)
1182 {
1183 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
1184 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
1185 WORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
1186 dec_state_t *ps_codec;
1187 dec_state_multi_core_t *ps_dec_state_multi_core;
1188
1189 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
1190 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
1191
1192
1193 ps_ip = (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
1194 ps_op = (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
1195 UNUSED(ps_ip);
1196 if(ps_codec->u2_header_done)
1197 {
1198 disp_wd = ps_codec->u2_horizontal_size;
1199 disp_ht = ps_codec->u2_vertical_size;
1200
1201 if(0 == ps_codec->u4_share_disp_buf)
1202 {
1203 buffer_wd = disp_wd;
1204 buffer_ht = disp_ht;
1205 }
1206 else
1207 {
1208 buffer_wd = ps_codec->u2_frame_width;
1209 buffer_ht = ps_codec->u2_frame_height;
1210 }
1211 }
1212 else
1213 {
1214
1215 disp_wd = ps_codec->u2_create_max_width;
1216 disp_ht = ps_codec->u2_create_max_height;
1217
1218 if(0 == ps_codec->u4_share_disp_buf)
1219 {
1220 buffer_wd = disp_wd;
1221 buffer_ht = disp_ht;
1222 }
1223 else
1224 {
1225 buffer_wd = ALIGN16(disp_wd);
1226 buffer_ht = ALIGN16(disp_ht);
1227
1228 }
1229 }
1230 if(ps_codec->u2_frame_width > buffer_wd)
1231 buffer_wd = ps_codec->u2_frame_width;
1232
1233 x_offset = 0;
1234 y_offset = 0;
1235
1236
1237 ps_op->u4_disp_wd[0] = disp_wd;
1238 ps_op->u4_disp_ht[0] = disp_ht;
1239 ps_op->u4_buffer_wd[0] = buffer_wd;
1240 ps_op->u4_buffer_ht[0] = buffer_ht;
1241 ps_op->u4_x_offset[0] = x_offset;
1242 ps_op->u4_y_offset[0] = y_offset;
1243
1244 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
1245 >> 1);
1246 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
1247 >> 1);
1248 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
1249 >> 1);
1250 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
1251 >> 1);
1252 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = (ps_op->u4_x_offset[0]
1253 >> 1);
1254 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = (ps_op->u4_y_offset[0]
1255 >> 1);
1256
1257 if((ps_codec->i4_chromaFormat == IV_YUV_420SP_UV)
1258 || (ps_codec->i4_chromaFormat == IV_YUV_420SP_VU))
1259 {
1260 ps_op->u4_disp_wd[2] = 0;
1261 ps_op->u4_disp_ht[2] = 0;
1262 ps_op->u4_buffer_wd[2] = 0;
1263 ps_op->u4_buffer_ht[2] = 0;
1264 ps_op->u4_x_offset[2] = 0;
1265 ps_op->u4_y_offset[2] = 0;
1266
1267 ps_op->u4_disp_wd[1] <<= 1;
1268 ps_op->u4_buffer_wd[1] <<= 1;
1269 ps_op->u4_x_offset[1] <<= 1;
1270 }
1271
1272 return IV_SUCCESS;
1273
1274 }
1275
impeg2d_api_function(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1276 IV_API_CALL_STATUS_T impeg2d_api_function (iv_obj_t *ps_dechdl, void *pv_api_ip,void *pv_api_op)
1277 {
1278 WORD32 i4_cmd;
1279 IV_API_CALL_STATUS_T u4_error_code;
1280 UWORD32 *pu4_api_ip;
1281
1282 u4_error_code = impeg2d_api_check_struct_sanity(ps_dechdl,pv_api_ip,pv_api_op);
1283 if(IV_SUCCESS != u4_error_code)
1284 {
1285 return u4_error_code;
1286 }
1287
1288
1289 pu4_api_ip = (UWORD32 *)pv_api_ip;
1290 i4_cmd = *(pu4_api_ip + 1);
1291
1292 switch(i4_cmd)
1293 {
1294
1295 case IV_CMD_GET_NUM_MEM_REC:
1296 u4_error_code = impeg2d_api_num_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1297 break;
1298
1299 case IV_CMD_FILL_NUM_MEM_REC:
1300 u4_error_code = impeg2d_api_fill_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1301 break;
1302
1303 case IV_CMD_INIT:
1304 u4_error_code = impeg2d_api_init(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1305 break;
1306
1307 case IVD_CMD_SET_DISPLAY_FRAME:
1308 u4_error_code = impeg2d_api_set_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1309 break;
1310
1311 case IVD_CMD_REL_DISPLAY_FRAME:
1312 u4_error_code = impeg2d_api_rel_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1313 break;
1314
1315 case IVD_CMD_VIDEO_DECODE:
1316 u4_error_code = impeg2d_api_entity(ps_dechdl, (void *)pv_api_ip,(void *)pv_api_op);
1317 break;
1318
1319 case IV_CMD_RETRIEVE_MEMREC:
1320 u4_error_code = impeg2d_api_retrieve_mem_rec(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1321 break;
1322
1323 case IVD_CMD_VIDEO_CTL:
1324 u4_error_code = impeg2d_api_ctl(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1325 break;
1326
1327 default:
1328 break;
1329 }
1330
1331 return(u4_error_code);
1332
1333 }
1334
1335 /*****************************************************************************/
1336 /* */
1337 /* Function Name : impeg2d_api_num_mem_rec */
1338 /* */
1339 /* Description : The function get the number mem records library needs */
1340 /* Inputs : Error message */
1341 /* Globals : None */
1342 /* Processing : Just prints error message to console */
1343 /* Outputs : Error mesage to the console */
1344 /* Returns : None */
1345 /* */
1346 /* Issues : <List any issues or problems with this function> */
1347 /* */
1348 /* Revision History: */
1349 /* */
1350 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1351 /* 23 09 2010 Hamsalekha Creation */
1352 /* */
1353 /*****************************************************************************/
1354
1355
impeg2d_api_num_mem_rec(void * pv_api_ip,void * pv_api_op)1356 IV_API_CALL_STATUS_T impeg2d_api_num_mem_rec(void *pv_api_ip,void *pv_api_op)
1357 {
1358 /* To Query No of Memory Records */
1359 impeg2d_num_mem_rec_ip_t *ps_query_mem_rec_ip;
1360 impeg2d_num_mem_rec_op_t *ps_query_mem_rec_op;
1361
1362 ps_query_mem_rec_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
1363 ps_query_mem_rec_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
1364
1365 UNUSED(ps_query_mem_rec_ip);
1366 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_size = sizeof(impeg2d_num_mem_rec_op_t);
1367
1368 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_num_mem_rec = (UWORD32)NUM_MEM_RECORDS;
1369
1370 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_error_code = IV_SUCCESS;
1371
1372
1373 return(IV_SUCCESS);
1374
1375 }
1376
1377
1378 /*****************************************************************************/
1379 /* */
1380 /* Function Name : impeg2d_api_fill_mem_rec */
1381 /* */
1382 /* Description : Thsi functions fills details of each mem record lib needs*/
1383 /* Inputs : Error message */
1384 /* Globals : None */
1385 /* Processing : Just prints error message to console */
1386 /* Outputs : Error mesage to the console */
1387 /* Returns : None */
1388 /* */
1389 /* Issues : <List any issues or problems with this function> */
1390 /* */
1391 /* Revision History: */
1392 /* */
1393 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1394 /* 23 09 2010 Hamsalekha Creation */
1395 /* */
1396 /*****************************************************************************/
1397
1398
impeg2d_api_fill_mem_rec(void * pv_api_ip,void * pv_api_op)1399 IV_API_CALL_STATUS_T impeg2d_api_fill_mem_rec(void *pv_api_ip,void *pv_api_op)
1400 {
1401
1402 impeg2d_fill_mem_rec_ip_t *ps_mem_q_ip;
1403 impeg2d_fill_mem_rec_op_t *ps_mem_q_op;
1404
1405
1406 ps_mem_q_ip = pv_api_ip;
1407 ps_mem_q_op = pv_api_op;
1408
1409
1410 impeg2d_fill_mem_rec((impeg2d_fill_mem_rec_ip_t *)ps_mem_q_ip,
1411 (impeg2d_fill_mem_rec_op_t *)ps_mem_q_op);
1412
1413
1414 return(IV_SUCCESS);
1415
1416 }
1417
1418
1419
1420 /*****************************************************************************/
1421 /* */
1422 /* Function Name : impeg2d_api_init */
1423 /* */
1424 /* Description : */
1425 /* Inputs : */
1426 /* Globals : */
1427 /* Processing : */
1428 /* Outputs : */
1429 /* Returns : */
1430 /* */
1431 /* Issues : */
1432 /* */
1433 /* Revision History: */
1434 /* */
1435 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1436 /* 17 09 2007 Rajendra C Y Draft */
1437 /* */
1438 /*****************************************************************************/
impeg2d_api_init(iv_obj_t * ps_dechdl,void * ps_ip,void * ps_op)1439 IV_API_CALL_STATUS_T impeg2d_api_init(iv_obj_t *ps_dechdl,
1440 void *ps_ip,
1441 void *ps_op)
1442 {
1443 UWORD32 i;
1444
1445 void *pv;
1446 UWORD32 u4_size;
1447
1448 dec_state_t *ps_dec_state;
1449 dec_state_multi_core_t *ps_dec_state_multi_core;
1450 UWORD32 u4_num_mem_rec;
1451 iv_mem_rec_t *ps_mem_rec ;
1452 iv_mem_rec_t *ps_frm_buf;
1453 iv_obj_t *ps_dec_handle;
1454 WORD32 i4_max_wd, i4_max_ht;
1455
1456 impeg2d_init_ip_t *ps_dec_init_ip;
1457 impeg2d_init_op_t *ps_dec_init_op;
1458 WORD32 i4_num_threads;
1459 UWORD32 u4_share_disp_buf, u4_chroma_format;
1460
1461 ps_dec_init_ip = (impeg2d_init_ip_t *)ps_ip;
1462 ps_dec_init_op = (impeg2d_init_op_t *)ps_op;
1463
1464 i4_max_wd = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1465 i4_max_ht = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1466
1467 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_share_disp_buf))
1468 {
1469 #ifndef LOGO_EN
1470 u4_share_disp_buf = ps_dec_init_ip->u4_share_disp_buf;
1471 #else
1472 u4_share_disp_buf = 0;
1473 #endif
1474 }
1475 else
1476 {
1477 u4_share_disp_buf = 0;
1478 }
1479
1480 u4_chroma_format = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1481
1482 if( (u4_chroma_format != IV_YUV_420P) &&
1483 (u4_chroma_format != IV_YUV_420SP_UV) &&
1484 (u4_chroma_format != IV_YUV_420SP_VU))
1485 {
1486 u4_share_disp_buf = 0;
1487 }
1488
1489
1490
1491
1492
1493 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1494 ps_mem_rec ++;
1495
1496
1497 ps_dec_init_op->s_ivd_init_op_t.u4_size = sizeof(impeg2d_init_op_t);
1498
1499
1500 /* Except memTab[0], all other memTabs are initialized to zero */
1501 for(i = 1; i < ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
1502 {
1503 memset(ps_mem_rec->pv_base,0,ps_mem_rec->u4_mem_size);
1504 ps_mem_rec++;
1505 }
1506
1507 /* Reinitializing memTab[0] memory base address */
1508 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1509
1510
1511 /* memTab[0] is for codec Handle,redundant currently not being used */
1512 ps_dec_handle = ps_mem_rec->pv_base;
1513 u4_num_mem_rec = 1;
1514 ps_mem_rec++;
1515
1516
1517
1518
1519
1520 /* decoder handle */
1521 ps_dec_state_multi_core = ps_mem_rec->pv_base;
1522 u4_num_mem_rec++;
1523 ps_mem_rec++;
1524
1525
1526 {
1527 ps_dec_handle->pv_codec_handle = (void *)ps_dec_state_multi_core; /* Initializing codec context */
1528
1529 ps_dechdl->pv_codec_handle = (void *)ps_dec_state_multi_core;
1530 ps_dechdl->pv_fxns = (void *)impeg2d_api_function;
1531 }
1532
1533
1534 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1535 {
1536 /*************************************************************************/
1537 /* For MPEG2 Decoder Context */
1538 /*************************************************************************/
1539 ps_dec_state = ps_mem_rec->pv_base;
1540
1541 ps_dec_state_multi_core->ps_dec_state[i4_num_threads] = ps_dec_state;
1542
1543 ps_dec_state->ps_dec_state_multi_core = ps_dec_state_multi_core;
1544
1545 ps_dec_state->i4_num_cores = 1;
1546 /* @ */ /* Used for storing MemRecords */
1547 u4_num_mem_rec++;
1548 ps_mem_rec++;
1549
1550 /* Thread handle */
1551 ps_dec_state->pv_codec_thread_handle = ps_mem_rec->pv_base;
1552 u4_num_mem_rec++;
1553 ps_mem_rec++;
1554
1555 /*************************************************************************/
1556 /* For Motion Compensation Buffers */
1557 /*************************************************************************/
1558 pv = ps_mem_rec->pv_base;
1559
1560 /* for mc_fw_buf.pu1_y */
1561
1562 ps_dec_state->s_mc_fw_buf.pu1_y = pv;
1563 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1564
1565 u4_size = sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1566 /* for mc_fw_buf.pu1_u */
1567
1568 ps_dec_state->s_mc_fw_buf.pu1_u = pv;
1569 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1570
1571 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1572
1573 /* for mc_fw_buf.pu1_v */
1574
1575 ps_dec_state->s_mc_fw_buf.pu1_v = pv;
1576 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1577
1578 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1579
1580 /* for mc_bk_buf.pu1_y */
1581
1582 ps_dec_state->s_mc_bk_buf.pu1_y = pv;
1583 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1584
1585 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1586
1587 /* for mc_bk_buf.pu1_u */
1588
1589 ps_dec_state->s_mc_bk_buf.pu1_u = pv;
1590 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1591
1592 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1593
1594 /* for mc_bk_buf.pu1_v */
1595
1596 ps_dec_state->s_mc_bk_buf.pu1_v = pv;
1597 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1598
1599 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1600
1601 /* for mc_buf.pu1_y */
1602
1603 ps_dec_state->s_mc_buf.pu1_y = pv;
1604 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1605
1606 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1607
1608 /* for mc_buf.pu1_u */
1609
1610 ps_dec_state->s_mc_buf.pu1_u = pv;
1611 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1612
1613 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1614
1615 /* for mc_buf.pu1_v */
1616
1617 ps_dec_state->s_mc_buf.pu1_v = pv;
1618
1619 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1620
1621 u4_num_mem_rec++;
1622 ps_mem_rec++;
1623
1624
1625
1626 ps_dec_state->pv_pic_buf_mg = 0;
1627
1628 /*************************************************************************/
1629 /* For saving stack context to support global error handling */
1630 /*************************************************************************/
1631 ps_dec_state->pv_stack_cntxt = ps_mem_rec->pv_base;
1632 u4_num_mem_rec++;
1633 ps_mem_rec++;
1634
1635 }
1636
1637
1638
1639
1640
1641 /*************************************************************************/
1642 /* For Picture Buffer Manager */
1643 /*************************************************************************/
1644 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1645
1646 ps_dec_state->pv_pic_buf_mg = ps_mem_rec->pv_base;
1647 ps_dec_state->pv_pic_buf_base = (UWORD8 *)ps_mem_rec->pv_base + sizeof(buf_mgr_t);
1648
1649 u4_num_mem_rec++;
1650 ps_mem_rec++;
1651
1652
1653
1654 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1655 {
1656
1657 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1658
1659
1660 /* --------------------------------------------------------------------- */
1661 /* Initializations */
1662
1663 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1664
1665
1666 {
1667 UWORD32 u4_max_frm_width,u4_max_frm_height;
1668
1669 u4_max_frm_width = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1670 u4_max_frm_height = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1671
1672 ps_dec_state->u2_create_max_width = u4_max_frm_width;
1673 ps_dec_state->u2_create_max_height = u4_max_frm_height;
1674
1675 ps_dec_state->i4_chromaFormat = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1676 ps_dec_state->u4_frm_buf_stride = 0 ;
1677 ps_dec_state->u2_frame_width = u4_max_frm_width;
1678 ps_dec_state->u2_picture_width = u4_max_frm_width;
1679 ps_dec_state->u2_horizontal_size = u4_max_frm_width;
1680
1681 ps_dec_state->u2_frame_height = u4_max_frm_height;
1682 ps_dec_state->u2_vertical_size = u4_max_frm_height;
1683 ps_dec_state->u4_share_disp_buf = u4_share_disp_buf;
1684 }
1685 }
1686
1687
1688 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1689
1690 if((ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1691 &&((ps_dec_state->u2_vertical_size & 0x1) != 0))
1692 {
1693 //printf("Error! Height should be multiple of 2 if Chroma format is 422ILE\n");
1694 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_CHROMA_FORMAT_HEIGHT_ERROR;
1695 return(IV_FAIL);
1696
1697
1698 }
1699
1700 /* --------------------------------------------------------------------- */
1701
1702
1703 /* ! */
1704 // picture buffer manager initialization will be done only for first thread
1705 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr);
1706 impeg2_buf_mgr_init((buf_mgr_t *)ps_dec_state->pv_pic_buf_mg);
1707
1708 /*************************************************************************/
1709 /* Internal Frame Buffers */
1710 /*************************************************************************/
1711
1712
1713 /* Set first frame to grey */
1714 {
1715 ps_frm_buf = ps_mem_rec;
1716 memset(ps_frm_buf->pv_base, 128, ps_frm_buf->u4_mem_size);
1717 ps_frm_buf++;
1718 }
1719
1720 if(0 == ps_dec_state->u4_share_disp_buf)
1721 {
1722 pic_buf_t *ps_pic_buf;
1723 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
1724 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1725 {
1726 UWORD8 *pu1_buf;
1727 pu1_buf = ps_mem_rec->pv_base;
1728
1729 ps_pic_buf->pu1_y = pu1_buf;
1730 pu1_buf += i4_max_ht * i4_max_wd;
1731
1732 ps_pic_buf->pu1_u = pu1_buf;
1733 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1734
1735 ps_pic_buf->pu1_v = pu1_buf;
1736 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1737
1738 ps_pic_buf->i4_buf_id = i;
1739
1740 ps_pic_buf->u1_used_as_ref = 0;
1741
1742 ps_pic_buf->u4_ts = 0;
1743
1744 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
1745 ps_mem_rec++;
1746 ps_pic_buf++;
1747 }
1748 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1749 }
1750 else if (ps_dec_state->i4_chromaFormat != IV_YUV_420P)
1751 {
1752 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1753 {
1754 ps_dec_state->pu1_chroma_ref_buf[i] = ps_mem_rec->pv_base;
1755 ps_mem_rec++;
1756 }
1757
1758 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1759 }
1760 else
1761 {
1762 ps_mem_rec+=NUM_INT_FRAME_BUFFERS;
1763 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1764 }
1765
1766
1767 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1768
1769
1770 ps_dec_state->pv_jobq_buf = ps_mem_rec->pv_base;
1771 ps_dec_state->i4_jobq_buf_size = ps_mem_rec->u4_mem_size;
1772 ps_mem_rec++;
1773
1774 if(u4_num_mem_rec > ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec)
1775 {
1776 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_NUM_MEM_REC_NOT_SUFFICIENT;
1777 return(IV_FAIL);
1778
1779 }
1780
1781 ps_dec_state->u1_flushfrm = 0;
1782 ps_dec_state->u1_flushcnt = 0;
1783 ps_dec_state->pv_jobq = impeg2_jobq_init(ps_dec_state->pv_jobq_buf, ps_dec_state->i4_jobq_buf_size);
1784
1785
1786 /*************************************************************************/
1787 /* MemTab[12] is used for storing TabRecords */
1788 /*************************************************************************/
1789 ps_dec_state->pv_memTab = (void *)ps_mem_rec->pv_base;
1790 memcpy(ps_mem_rec->pv_base,ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location, ps_mem_rec->u4_mem_size);
1791 /* Updating in Decoder Context with memRecords */
1792 u4_num_mem_rec++;
1793 ps_mem_rec++;
1794 ps_dec_state->u4_num_mem_records = u4_num_mem_rec;
1795
1796
1797 ps_dec_state->u4_num_frames_decoded = 0;
1798 ps_dec_state->aps_ref_pics[0] = NULL;
1799 ps_dec_state->aps_ref_pics[1] = NULL;
1800
1801 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IV_SUCCESS;
1802 impeg2d_init_arch(ps_dec_state);
1803
1804 impeg2d_init_function_ptr(ps_dec_state);
1805
1806 return(IV_SUCCESS);
1807 }
1808
1809 /*****************************************************************************/
1810 /* */
1811 /* Function Name : impeg2d_api_retrieve_mem_rec */
1812 /* */
1813 /* Description : */
1814 /* */
1815 /* Inputs : */
1816 /* Globals : <Does it use any global variables?> */
1817 /* Outputs : */
1818 /* Returns : void */
1819 /* */
1820 /* Issues : none */
1821 /* */
1822 /* Revision History: */
1823 /* */
1824 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1825 /* 22 10 2008 100356 Draft */
1826 /* */
1827 /*****************************************************************************/
impeg2d_api_retrieve_mem_rec(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1828 IV_API_CALL_STATUS_T impeg2d_api_retrieve_mem_rec(iv_obj_t *ps_dechdl,
1829 void *pv_api_ip,
1830 void *pv_api_op)
1831 {
1832 UWORD32 u4_i;
1833 dec_state_t *ps_dec_state;
1834 dec_state_multi_core_t *ps_dec_state_multi_core;
1835 iv_mem_rec_t *ps_mem_rec;
1836 iv_mem_rec_t *ps_temp_rec;
1837
1838
1839
1840 impeg2d_retrieve_mem_rec_ip_t *ps_retr_mem_rec_ip;
1841 impeg2d_retrieve_mem_rec_op_t *ps_retr_mem_rec_op;
1842
1843 ps_retr_mem_rec_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
1844 ps_retr_mem_rec_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
1845
1846 ps_mem_rec = ps_retr_mem_rec_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
1847 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1848 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1849 ps_temp_rec = ps_dec_state->pv_memTab;
1850
1851 for(u4_i = 0; u4_i < (ps_dec_state->u4_num_mem_records);u4_i++)
1852 {
1853 ps_mem_rec[u4_i].u4_mem_size = ps_temp_rec[u4_i].u4_mem_size;
1854 ps_mem_rec[u4_i].u4_mem_alignment = ps_temp_rec[u4_i].u4_mem_alignment;
1855 ps_mem_rec[u4_i].e_mem_type = ps_temp_rec[u4_i].e_mem_type;
1856 ps_mem_rec[u4_i].pv_base = ps_temp_rec[u4_i].pv_base;
1857 }
1858
1859 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = IV_SUCCESS;
1860 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_num_mem_rec_filled = ps_dec_state->u4_num_mem_records;
1861
1862 impeg2_jobq_deinit(ps_dec_state->pv_jobq);
1863 IMPEG2D_PRINT_STATISTICS();
1864
1865
1866 return(IV_SUCCESS);
1867
1868 }
1869
1870 /*****************************************************************************/
1871 /* */
1872 /* Function Name : impeg2d_api_ctl */
1873 /* */
1874 /* Description : */
1875 /* */
1876 /* Inputs : */
1877 /* Globals : <Does it use any global variables?> */
1878 /* Outputs : */
1879 /* Returns : void */
1880 /* */
1881 /* Issues : none */
1882 /* */
1883 /* Revision History: */
1884 /* */
1885 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1886 /* 22 10 2008 100356 Draft */
1887 /* */
1888 /*****************************************************************************/
impeg2d_api_ctl(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1889 IV_API_CALL_STATUS_T impeg2d_api_ctl(iv_obj_t *ps_dechdl,
1890 void *pv_api_ip,
1891 void *pv_api_op)
1892 {
1893 WORD32 i4_sub_cmd;
1894 UWORD32 *pu4_api_ip;
1895 IV_API_CALL_STATUS_T u4_error_code;
1896
1897 pu4_api_ip = (UWORD32 *)pv_api_ip;
1898 i4_sub_cmd = *(pu4_api_ip + 2);
1899
1900 switch(i4_sub_cmd)
1901 {
1902 case IVD_CMD_CTL_GETPARAMS:
1903 u4_error_code = impeg2d_api_get_status(ps_dechdl, (void *)pv_api_ip,
1904 (void *)pv_api_op);
1905 break;
1906
1907 case IVD_CMD_CTL_SETPARAMS:
1908 u4_error_code = impeg2d_api_set_params(ps_dechdl, (void *)pv_api_ip,
1909 (void *)pv_api_op);
1910 break;
1911
1912 case IVD_CMD_CTL_RESET:
1913 u4_error_code = impeg2d_api_reset(ps_dechdl, (void *)pv_api_ip,
1914 (void *)pv_api_op);
1915 break;
1916
1917 case IVD_CMD_CTL_SETDEFAULT:
1918 u4_error_code = impeg2d_api_set_default(ps_dechdl,
1919 (void *)pv_api_ip,
1920 (void *)pv_api_op);
1921 break;
1922
1923 case IVD_CMD_CTL_FLUSH:
1924 u4_error_code = impeg2d_api_set_flush_mode(ps_dechdl,
1925 (void *)pv_api_ip,
1926 (void *)pv_api_op);
1927 break;
1928
1929 case IVD_CMD_CTL_GETBUFINFO:
1930 u4_error_code = impeg2d_api_get_buf_info(ps_dechdl,
1931 (void *)pv_api_ip,
1932 (void *)pv_api_op);
1933 break;
1934
1935 case IVD_CMD_CTL_GETVERSION:
1936 u4_error_code = impeg2d_api_get_version(ps_dechdl, (void *)pv_api_ip,
1937 (void *)pv_api_op);
1938 break;
1939
1940 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
1941 u4_error_code = impeg2d_api_set_num_cores(ps_dechdl,
1942 (void *)pv_api_ip,
1943 (void *)pv_api_op);
1944 break;
1945
1946 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
1947 u4_error_code = impeg2d_get_frame_dimensions(ps_dechdl,
1948 (void *)pv_api_ip,
1949 (void *)pv_api_op);
1950 break;
1951
1952 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
1953 u4_error_code = impeg2d_set_processor(ps_dechdl, (void *)pv_api_ip,
1954 (void *)pv_api_op);
1955 break;
1956
1957 default:
1958 u4_error_code = IV_FAIL;
1959 break;
1960 }
1961
1962 return (u4_error_code);
1963
1964 }
1965
1966 /*****************************************************************************/
1967 /* */
1968 /* Function Name : impeg2d_api_check_struct_sanity */
1969 /* */
1970 /* Description : */
1971 /* */
1972 /* Inputs : */
1973 /* Globals : <Does it use any global variables?> */
1974 /* Outputs : */
1975 /* Returns : void */
1976 /* */
1977 /* Issues : none */
1978 /* */
1979 /* Revision History: */
1980 /* */
1981 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1982 /* 22 10 2008 100356 Draft */
1983 /* */
1984 /*****************************************************************************/
impeg2d_api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)1985 IV_API_CALL_STATUS_T impeg2d_api_check_struct_sanity(iv_obj_t *ps_handle,
1986 void *pv_api_ip,
1987 void *pv_api_op)
1988 {
1989 WORD32 i4_cmd;
1990 UWORD32 *pu4_api_ip;
1991 UWORD32 *pu4_api_op;
1992 WORD32 i,j;
1993
1994 if(NULL == pv_api_op)
1995 return(IV_FAIL);
1996
1997 if(NULL == pv_api_ip)
1998 return(IV_FAIL);
1999
2000 pu4_api_ip = (UWORD32 *)pv_api_ip;
2001 pu4_api_op = (UWORD32 *)pv_api_op;
2002 i4_cmd = (IVD_API_COMMAND_TYPE_T)*(pu4_api_ip + 1);
2003
2004 /* error checks on handle */
2005 switch(i4_cmd)
2006 {
2007 case IV_CMD_GET_NUM_MEM_REC:
2008 case IV_CMD_FILL_NUM_MEM_REC:
2009 break;
2010 case IV_CMD_INIT:
2011 if(ps_handle == NULL)
2012 {
2013 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2014 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2015 return IV_FAIL;
2016 }
2017
2018 if(ps_handle->u4_size != sizeof(iv_obj_t))
2019 {
2020 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2021 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2022 return IV_FAIL;
2023 }
2024 break;
2025 case IVD_CMD_GET_DISPLAY_FRAME:
2026 case IVD_CMD_VIDEO_DECODE:
2027 case IV_CMD_RETRIEVE_MEMREC:
2028 case IVD_CMD_SET_DISPLAY_FRAME:
2029 case IVD_CMD_REL_DISPLAY_FRAME:
2030 case IVD_CMD_VIDEO_CTL:
2031 {
2032 if(ps_handle == NULL)
2033 {
2034 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2035 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2036 return IV_FAIL;
2037 }
2038
2039 if(ps_handle->u4_size != sizeof(iv_obj_t))
2040 {
2041 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2042 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2043 return IV_FAIL;
2044 }
2045 if(ps_handle->pv_fxns != impeg2d_api_function)
2046 {
2047 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2048 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2049 return IV_FAIL;
2050 }
2051
2052 if(ps_handle->pv_codec_handle == NULL)
2053 {
2054 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2055 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2056 return IV_FAIL;
2057 }
2058 }
2059 break;
2060 default:
2061 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2062 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
2063 return IV_FAIL;
2064 }
2065
2066 switch(i4_cmd)
2067 {
2068 case IV_CMD_GET_NUM_MEM_REC:
2069 {
2070 impeg2d_num_mem_rec_ip_t *ps_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
2071 impeg2d_num_mem_rec_op_t *ps_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
2072 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0;
2073
2074 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size != sizeof(impeg2d_num_mem_rec_ip_t))
2075 {
2076 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2077 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2078 return(IV_FAIL);
2079 }
2080
2081 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size != sizeof(impeg2d_num_mem_rec_op_t))
2082 {
2083 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2084 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2085 return(IV_FAIL);
2086 }
2087 }
2088 break;
2089 case IV_CMD_FILL_NUM_MEM_REC:
2090 {
2091 impeg2d_fill_mem_rec_ip_t *ps_ip = (impeg2d_fill_mem_rec_ip_t *)pv_api_ip;
2092 impeg2d_fill_mem_rec_op_t *ps_op = (impeg2d_fill_mem_rec_op_t *)pv_api_op;
2093 iv_mem_rec_t *ps_mem_rec;
2094
2095 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
2096
2097 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size != sizeof(impeg2d_fill_mem_rec_ip_t))
2098 {
2099 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2100 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2101 return(IV_FAIL);
2102 }
2103
2104 if(ps_op->s_ivd_fill_mem_rec_op_t.u4_size != sizeof(impeg2d_fill_mem_rec_op_t))
2105 {
2106 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2107 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2108 return(IV_FAIL);
2109 }
2110
2111 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd < MIN_WIDTH)
2112 {
2113 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2114 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2115 return(IV_FAIL);
2116 }
2117
2118 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd > MAX_WIDTH)
2119 {
2120 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2121 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2122 return(IV_FAIL);
2123 }
2124
2125 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht < MIN_HEIGHT)
2126 {
2127 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2128 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2129 return(IV_FAIL);
2130 }
2131
2132 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht > MAX_HEIGHT)
2133 {
2134 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2135 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2136 return(IV_FAIL);
2137 }
2138
2139 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location)
2140 {
2141 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2142 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2143 return(IV_FAIL);
2144 }
2145
2146 /* check memrecords sizes are correct */
2147 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
2148 for(i=0;i<NUM_MEM_RECORDS;i++)
2149 {
2150 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2151 {
2152 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2153 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2154 return IV_FAIL;
2155 }
2156 }
2157 }
2158 break;
2159
2160 case IV_CMD_INIT:
2161 {
2162 impeg2d_init_ip_t *ps_ip = (impeg2d_init_ip_t *)pv_api_ip;
2163 impeg2d_init_op_t *ps_op = (impeg2d_init_op_t *)pv_api_op;
2164 iv_mem_rec_t *ps_mem_rec;
2165 UWORD32 u4_tot_num_mem_recs;
2166
2167 ps_op->s_ivd_init_op_t.u4_error_code = 0;
2168
2169 if(ps_ip->s_ivd_init_ip_t.u4_size != sizeof(impeg2d_init_ip_t))
2170 {
2171 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2172 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2173 return(IV_FAIL);
2174 }
2175
2176 if(ps_op->s_ivd_init_op_t.u4_size != sizeof(impeg2d_init_op_t))
2177 {
2178 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2179 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2180 return(IV_FAIL);
2181 }
2182
2183 u4_tot_num_mem_recs = NUM_MEM_RECORDS;
2184
2185
2186
2187
2188 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec > u4_tot_num_mem_recs)
2189 {
2190 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2191 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_NOT_SUFFICIENT;
2192 return(IV_FAIL);
2193 }
2194
2195 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd < MIN_WIDTH)
2196 {
2197 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2198 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2199 return(IV_FAIL);
2200 }
2201
2202 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd > MAX_WIDTH)
2203 {
2204 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2205 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2206 return(IV_FAIL);
2207 }
2208
2209 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht < MIN_HEIGHT)
2210 {
2211 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2212 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2213 return(IV_FAIL);
2214 }
2215
2216 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht > MAX_HEIGHT)
2217 {
2218 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2219 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2220 return(IV_FAIL);
2221 }
2222
2223 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location)
2224 {
2225 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2226 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2227 return(IV_FAIL);
2228 }
2229
2230 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) &&
2231 (ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_422ILE)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_UV)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_VU))
2232 {
2233 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2234 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
2235 return(IV_FAIL);
2236 }
2237
2238 /* verify number of mem records */
2239 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < NUM_MEM_RECORDS)
2240 {
2241 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2242 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT;
2243 return IV_FAIL;
2244 }
2245
2246 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location;
2247 /* verify wether first memrecord is handle or not */
2248 /*
2249 if(ps_mem_rec->pv_base != ps_handle)
2250 {
2251 // indicate the incorrect handle error
2252 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2253 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INVALID_HANDLE;
2254 return IV_FAIL;
2255 }
2256 */
2257 /* check memrecords sizes are correct */
2258 for(i=0;i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec ; i++)
2259 {
2260 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2261 {
2262 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2263 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2264 return IV_FAIL;
2265 }
2266 }
2267
2268 /* verify memtabs for overlapping regions */
2269 {
2270 UWORD8 *pau1_start[NUM_MEM_RECORDS];
2271 UWORD8 *pau1_end[NUM_MEM_RECORDS];
2272
2273
2274 pau1_start[0] = (UWORD8 *)(ps_mem_rec[0].pv_base);
2275 pau1_end[0] = (UWORD8 *)(ps_mem_rec[0].pv_base) + ps_mem_rec[0].u4_mem_size - 1;
2276 for(i = 1; i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
2277 {
2278 /* This array is populated to check memtab overlapp */
2279 pau1_start[i] = (UWORD8 *)(ps_mem_rec[i].pv_base);
2280 pau1_end[i] = (UWORD8 *)(ps_mem_rec[i].pv_base) + ps_mem_rec[i].u4_mem_size - 1;
2281
2282 for(j = 0; j < i; j++)
2283 {
2284 if((pau1_start[i] >= pau1_start[j]) && (pau1_start[i] <= pau1_end[j]))
2285 {
2286 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2287 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2288 return IV_FAIL;
2289 }
2290
2291 if((pau1_end[i] >= pau1_start[j]) && (pau1_end[i] <= pau1_end[j]))
2292 {
2293 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2294 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2295 return IV_FAIL;
2296 }
2297
2298 if((pau1_start[i] < pau1_start[j]) && (pau1_end[i] > pau1_end[j]))
2299 {
2300 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2301 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2302 return IV_FAIL;
2303 }
2304 }
2305 }
2306 }
2307
2308
2309
2310
2311 {
2312 iv_mem_rec_t as_mem_rec_ittiam_api[NUM_MEM_RECORDS];
2313
2314 impeg2d_fill_mem_rec_ip_t s_fill_mem_rec_ip;
2315 impeg2d_fill_mem_rec_op_t s_fill_mem_rec_op;
2316 IV_API_CALL_STATUS_T e_status;
2317 WORD32 i4_num_memrec;
2318 {
2319
2320 iv_num_mem_rec_ip_t s_no_of_mem_rec_query_ip;
2321 iv_num_mem_rec_op_t s_no_of_mem_rec_query_op;
2322
2323
2324 s_no_of_mem_rec_query_ip.u4_size = sizeof(iv_num_mem_rec_ip_t);
2325 s_no_of_mem_rec_query_op.u4_size = sizeof(iv_num_mem_rec_op_t);
2326
2327 s_no_of_mem_rec_query_ip.e_cmd = IV_CMD_GET_NUM_MEM_REC;
2328 impeg2d_api_function(NULL,
2329 (void *)&s_no_of_mem_rec_query_ip,
2330 (void *)&s_no_of_mem_rec_query_op);
2331
2332 i4_num_memrec = s_no_of_mem_rec_query_op.u4_num_mem_rec;
2333
2334
2335
2336 }
2337
2338
2339 /* initialize mem records array with sizes */
2340 for(i = 0; i < i4_num_memrec; i++)
2341 {
2342 as_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
2343 }
2344
2345 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = sizeof(impeg2d_fill_mem_rec_ip_t);
2346 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
2347 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd;
2348 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht;
2349 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = as_mem_rec_ittiam_api;
2350 s_fill_mem_rec_ip.u4_share_disp_buf = ps_ip->u4_share_disp_buf;
2351 s_fill_mem_rec_ip.e_output_format = ps_ip->s_ivd_init_ip_t.e_output_format;
2352 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = sizeof(impeg2d_fill_mem_rec_op_t);
2353
2354
2355 e_status = impeg2d_api_function(NULL,
2356 (void *)&s_fill_mem_rec_ip,
2357 (void *)&s_fill_mem_rec_op);
2358 if(IV_FAIL == e_status)
2359 {
2360 ps_op->s_ivd_init_op_t.u4_error_code = s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code;
2361 return(IV_FAIL);
2362 }
2363
2364
2365
2366 for(i = 0; i < i4_num_memrec; i ++)
2367 {
2368 if(ps_mem_rec[i].pv_base == NULL)
2369 {
2370 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2371 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_BASE_NULL;
2372 return IV_FAIL;
2373 }
2374 #ifdef CHECK_ALIGN
2375
2376 if((UWORD32)(ps_mem_rec[i].pv_base) & (ps_mem_rec[i].u4_mem_alignment - 1))
2377 {
2378 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2379 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2380 return IV_FAIL;
2381 }
2382 #endif //CHECK_ALIGN
2383 if(ps_mem_rec[i].u4_mem_alignment != as_mem_rec_ittiam_api[i].u4_mem_alignment)
2384 {
2385 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2386 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2387 return IV_FAIL;
2388 }
2389
2390 if(ps_mem_rec[i].u4_mem_size < as_mem_rec_ittiam_api[i].u4_mem_size)
2391 {
2392 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2393 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE;
2394 return IV_FAIL;
2395 }
2396
2397 if(ps_mem_rec[i].e_mem_type != as_mem_rec_ittiam_api[i].e_mem_type)
2398 {
2399 if (IV_EXTERNAL_CACHEABLE_SCRATCH_MEM == as_mem_rec_ittiam_api[i].e_mem_type)
2400 {
2401 if (IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM == ps_mem_rec[i].e_mem_type)
2402 {
2403 continue;
2404 }
2405 }
2406 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2407 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE;
2408 return IV_FAIL;
2409 }
2410 }
2411 }
2412
2413
2414 }
2415 break;
2416
2417 case IVD_CMD_GET_DISPLAY_FRAME:
2418 {
2419 impeg2d_get_display_frame_ip_t *ps_ip = (impeg2d_get_display_frame_ip_t *)pv_api_ip;
2420 impeg2d_get_display_frame_op_t *ps_op = (impeg2d_get_display_frame_op_t *)pv_api_op;
2421
2422 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
2423
2424 if(ps_ip->s_ivd_get_display_frame_ip_t.u4_size != sizeof(impeg2d_get_display_frame_ip_t))
2425 {
2426 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2427 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2428 return(IV_FAIL);
2429 }
2430
2431 if(ps_op->s_ivd_get_display_frame_op_t.u4_size != sizeof(impeg2d_get_display_frame_op_t))
2432 {
2433 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2434 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2435 return(IV_FAIL);
2436 }
2437
2438 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs == 0)
2439 {
2440 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2441 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2442 return IV_FAIL;
2443 }
2444
2445 for(i = 0; i< (WORD32)ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs;i++)
2446 {
2447 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.pu1_bufs[i] == NULL)
2448 {
2449 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2450 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2451 return IV_FAIL;
2452 }
2453
2454 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2455 {
2456 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2457 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2458 return IV_FAIL;
2459 }
2460 /*
2461 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2462 {
2463 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2464 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2465 return IV_FAIL;
2466 }
2467 */
2468 }
2469 }
2470 break;
2471 case IVD_CMD_REL_DISPLAY_FRAME:
2472 {
2473 impeg2d_rel_display_frame_ip_t *ps_ip = (impeg2d_rel_display_frame_ip_t *)pv_api_ip;
2474 impeg2d_rel_display_frame_op_t *ps_op = (impeg2d_rel_display_frame_op_t *)pv_api_op;
2475
2476 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
2477
2478 if ((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(impeg2d_rel_display_frame_ip_t))
2479 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(ivd_rel_display_frame_ip_t)))
2480 {
2481 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2482 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2483 return(IV_FAIL);
2484 }
2485
2486 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(impeg2d_rel_display_frame_op_t)) &&
2487 (ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(ivd_rel_display_frame_op_t)))
2488 {
2489 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2490 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2491 return(IV_FAIL);
2492 }
2493
2494 }
2495 break;
2496
2497
2498 case IVD_CMD_SET_DISPLAY_FRAME:
2499 {
2500 impeg2d_set_display_frame_ip_t *ps_ip = (impeg2d_set_display_frame_ip_t *)pv_api_ip;
2501 impeg2d_set_display_frame_op_t *ps_op = (impeg2d_set_display_frame_op_t *)pv_api_op;
2502 UWORD32 j, i;
2503
2504 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
2505
2506 if ((ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(impeg2d_set_display_frame_ip_t))
2507 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(ivd_set_display_frame_ip_t)))
2508 {
2509 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2510 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2511 return(IV_FAIL);
2512 }
2513
2514 if((ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(impeg2d_set_display_frame_op_t)) &&
2515 (ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(ivd_set_display_frame_op_t)))
2516 {
2517 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2518 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2519 return(IV_FAIL);
2520 }
2521
2522 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
2523 {
2524 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2525 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2526 return IV_FAIL;
2527 }
2528
2529 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; j++)
2530 {
2531 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs == 0)
2532 {
2533 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2534 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2535 return IV_FAIL;
2536 }
2537
2538 for(i=0;i< ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;i++)
2539 {
2540 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] == NULL)
2541 {
2542 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2543 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2544 return IV_FAIL;
2545 }
2546
2547 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] == 0)
2548 {
2549 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2550 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2551 return IV_FAIL;
2552 }
2553 }
2554 }
2555 }
2556 break;
2557
2558 case IVD_CMD_VIDEO_DECODE:
2559 {
2560 impeg2d_video_decode_ip_t *ps_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
2561 impeg2d_video_decode_op_t *ps_op = (impeg2d_video_decode_op_t *)pv_api_op;
2562
2563 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
2564
2565 if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(impeg2d_video_decode_ip_t))
2566 {
2567 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2568 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2569 return(IV_FAIL);
2570 }
2571
2572 if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(impeg2d_video_decode_op_t))
2573 {
2574 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2575 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2576 return(IV_FAIL);
2577 }
2578
2579 }
2580 break;
2581
2582 case IV_CMD_RETRIEVE_MEMREC:
2583 {
2584 impeg2d_retrieve_mem_rec_ip_t *ps_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
2585 impeg2d_retrieve_mem_rec_op_t *ps_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
2586 iv_mem_rec_t *ps_mem_rec;
2587
2588 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0;
2589
2590 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_ip_t))
2591 {
2592 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2593 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2594 return(IV_FAIL);
2595 }
2596
2597 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_op_t))
2598 {
2599 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2600 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2601 return(IV_FAIL);
2602 }
2603
2604 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
2605 /* check memrecords sizes are correct */
2606 for(i=0;i < NUM_MEM_RECORDS ; i++)
2607 {
2608 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2609 {
2610 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2611 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2612 return IV_FAIL;
2613 }
2614 }
2615 }
2616 break;
2617
2618 case IVD_CMD_VIDEO_CTL:
2619 {
2620 UWORD32 *pu4_ptr_cmd;
2621 UWORD32 u4_sub_command;
2622
2623 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
2624 pu4_ptr_cmd += 2;
2625 u4_sub_command = *pu4_ptr_cmd;
2626
2627 switch(u4_sub_command)
2628 {
2629 case IVD_CMD_CTL_SETPARAMS:
2630 {
2631 impeg2d_ctl_set_config_ip_t *ps_ip;
2632 impeg2d_ctl_set_config_op_t *ps_op;
2633 ps_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
2634 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2635
2636 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2637
2638 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size != sizeof(impeg2d_ctl_set_config_ip_t))
2639 {
2640 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2641 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2642 return IV_FAIL;
2643 }
2644 }
2645 case IVD_CMD_CTL_SETDEFAULT:
2646 {
2647 impeg2d_ctl_set_config_op_t *ps_op;
2648 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2649 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2650
2651 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size != sizeof(impeg2d_ctl_set_config_op_t))
2652 {
2653 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2654 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2655 return IV_FAIL;
2656 }
2657 }
2658 break;
2659
2660 case IVD_CMD_CTL_GETPARAMS:
2661 {
2662 impeg2d_ctl_getstatus_ip_t *ps_ip;
2663 impeg2d_ctl_getstatus_op_t *ps_op;
2664
2665 ps_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
2666 ps_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
2667
2668 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code = 0;
2669
2670 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size != sizeof(impeg2d_ctl_getstatus_ip_t))
2671 {
2672 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2673 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2674 return IV_FAIL;
2675 }
2676 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size != sizeof(impeg2d_ctl_getstatus_op_t))
2677 {
2678 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2679 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2680 return IV_FAIL;
2681 }
2682 }
2683 break;
2684
2685 case IVD_CMD_CTL_GETBUFINFO:
2686 {
2687 impeg2d_ctl_getbufinfo_ip_t *ps_ip;
2688 impeg2d_ctl_getbufinfo_op_t *ps_op;
2689 ps_ip = (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
2690 ps_op = (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
2691
2692 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = 0;
2693
2694 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_ip_t))
2695 {
2696 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2697 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2698 return IV_FAIL;
2699 }
2700 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_op_t))
2701 {
2702 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2703 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2704 return IV_FAIL;
2705 }
2706 }
2707 break;
2708
2709 case IVD_CMD_CTL_GETVERSION:
2710 {
2711 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
2712 impeg2d_ctl_getversioninfo_op_t *ps_op;
2713 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
2714 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
2715
2716 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = 0;
2717
2718 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_ip_t))
2719 {
2720 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2721 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2722 return IV_FAIL;
2723 }
2724 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_op_t))
2725 {
2726 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2727 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2728 return IV_FAIL;
2729 }
2730 }
2731 break;
2732
2733 case IVD_CMD_CTL_FLUSH:
2734 {
2735 impeg2d_ctl_flush_ip_t *ps_ip;
2736 impeg2d_ctl_flush_op_t *ps_op;
2737 ps_ip = (impeg2d_ctl_flush_ip_t *)pv_api_ip;
2738 ps_op = (impeg2d_ctl_flush_op_t *)pv_api_op;
2739
2740 ps_op->s_ivd_ctl_flush_op_t.u4_error_code = 0;
2741
2742 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size != sizeof(impeg2d_ctl_flush_ip_t))
2743 {
2744 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2745 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2746 return IV_FAIL;
2747 }
2748 if(ps_op->s_ivd_ctl_flush_op_t.u4_size != sizeof(impeg2d_ctl_flush_op_t))
2749 {
2750 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2751 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2752 return IV_FAIL;
2753 }
2754 }
2755 break;
2756
2757 case IVD_CMD_CTL_RESET:
2758 {
2759 impeg2d_ctl_reset_ip_t *ps_ip;
2760 impeg2d_ctl_reset_op_t *ps_op;
2761 ps_ip = (impeg2d_ctl_reset_ip_t *)pv_api_ip;
2762 ps_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
2763
2764 ps_op->s_ivd_ctl_reset_op_t.u4_error_code = 0;
2765
2766 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size != sizeof(impeg2d_ctl_reset_ip_t))
2767 {
2768 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2769 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2770 return IV_FAIL;
2771 }
2772 if(ps_op->s_ivd_ctl_reset_op_t.u4_size != sizeof(impeg2d_ctl_reset_op_t))
2773 {
2774 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2775 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2776 return IV_FAIL;
2777 }
2778 }
2779 break;
2780
2781 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2782 {
2783 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
2784 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
2785
2786 ps_ip =
2787 (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
2788 ps_op =
2789 (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
2790
2791 if(ps_ip->u4_size
2792 != sizeof(impeg2d_ctl_get_frame_dimensions_ip_t))
2793 {
2794 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2795 ps_op->u4_error_code |=
2796 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2797 return IV_FAIL;
2798 }
2799
2800 if(ps_op->u4_size
2801 != sizeof(impeg2d_ctl_get_frame_dimensions_op_t))
2802 {
2803 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2804 ps_op->u4_error_code |=
2805 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2806 return IV_FAIL;
2807 }
2808
2809 break;
2810 }
2811
2812 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
2813 {
2814 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
2815 impeg2d_ctl_set_num_cores_op_t *ps_op;
2816
2817 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
2818 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
2819
2820 if(ps_ip->u4_size
2821 != sizeof(impeg2d_ctl_set_num_cores_ip_t))
2822 {
2823 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2824 ps_op->u4_error_code |=
2825 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2826 return IV_FAIL;
2827 }
2828
2829 if(ps_op->u4_size
2830 != sizeof(impeg2d_ctl_set_num_cores_op_t))
2831 {
2832 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2833 ps_op->u4_error_code |=
2834 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2835 return IV_FAIL;
2836 }
2837
2838 #ifdef MULTICORE
2839 if((ps_ip->u4_num_cores < 1) || (ps_ip->u4_num_cores > MAX_THREADS))
2840 #else
2841 if(ps_ip->u4_num_cores != 1)
2842 #endif
2843 {
2844 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2845 return IV_FAIL;
2846 }
2847 break;
2848 }
2849 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
2850 {
2851 impeg2d_ctl_set_processor_ip_t *ps_ip;
2852 impeg2d_ctl_set_processor_op_t *ps_op;
2853
2854 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
2855 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
2856
2857 if(ps_ip->u4_size
2858 != sizeof(impeg2d_ctl_set_processor_ip_t))
2859 {
2860 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2861 ps_op->u4_error_code |=
2862 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2863 return IV_FAIL;
2864 }
2865
2866 if(ps_op->u4_size
2867 != sizeof(impeg2d_ctl_set_processor_op_t))
2868 {
2869 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2870 ps_op->u4_error_code |=
2871 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2872 return IV_FAIL;
2873 }
2874
2875 break;
2876 }
2877 default:
2878 break;
2879
2880 }
2881 }
2882 break;
2883
2884 default:
2885 { *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2886 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
2887 return IV_FAIL;
2888 }
2889
2890
2891 }
2892
2893 return IV_SUCCESS;
2894 }
2895
2896 /*****************************************************************************/
2897 /* */
2898 /* Function Name : impeg2d_api_entity */
2899 /* */
2900 /* Description : */
2901 /* */
2902 /* Inputs : */
2903 /* Globals : <Does it use any global variables?> */
2904 /* Outputs : */
2905 /* Returns : void */
2906 /* */
2907 /* Issues : none */
2908 /* */
2909 /* Revision History: */
2910 /* */
2911 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2912 /* 22 10 2008 100356 Draft */
2913 /* */
2914 /*****************************************************************************/
2915
2916
impeg2d_api_entity(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)2917 IV_API_CALL_STATUS_T impeg2d_api_entity(iv_obj_t *ps_dechdl,
2918 void *pv_api_ip,
2919 void *pv_api_op)
2920 {
2921 iv_obj_t *ps_dec_handle;
2922 dec_state_t *ps_dec_state;
2923 dec_state_multi_core_t *ps_dec_state_multi_core;
2924
2925 impeg2d_video_decode_ip_t *ps_dec_ip;
2926
2927 impeg2d_video_decode_op_t *ps_dec_op;
2928 WORD32 bytes_remaining;
2929 pic_buf_t *ps_disp_pic;
2930
2931
2932
2933 ps_dec_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
2934 ps_dec_op = (impeg2d_video_decode_op_t *)pv_api_op;
2935
2936 memset(ps_dec_op,0,sizeof(impeg2d_video_decode_op_t));
2937
2938 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
2939 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
2940 bytes_remaining = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
2941
2942 ps_dec_handle = (iv_obj_t *)ps_dechdl;
2943
2944 if(ps_dechdl == NULL)
2945 {
2946 return(IV_FAIL);
2947 }
2948
2949
2950
2951 ps_dec_state_multi_core = ps_dec_handle->pv_codec_handle;
2952 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
2953
2954 ps_dec_state->ps_disp_frm_buf = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
2955 if(0 == ps_dec_state->u4_share_disp_buf)
2956 {
2957 ps_dec_state->ps_disp_frm_buf->pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
2958 ps_dec_state->ps_disp_frm_buf->pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
2959 ps_dec_state->ps_disp_frm_buf->pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
2960 }
2961
2962 ps_dec_state->ps_disp_pic = NULL;
2963 ps_dec_state->i4_frame_decoded = 0;
2964 /*rest bytes consumed */
2965 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = 0;
2966
2967 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IV_SUCCESS;
2968
2969 if((ps_dec_ip->s_ivd_video_decode_ip_t.pv_stream_buffer == NULL)&&(ps_dec_state->u1_flushfrm==0))
2970 {
2971 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2972 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
2973 return IV_FAIL;
2974 }
2975
2976
2977 if (ps_dec_state->u4_num_frames_decoded > NUM_FRAMES_LIMIT)
2978 {
2979 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IMPEG2D_SAMPLE_VERSION_LIMIT_ERR;
2980 return(IV_FAIL);
2981 }
2982
2983 if(((0 == ps_dec_state->u2_header_done) || (ps_dec_state->u2_decode_header == 1)) && (ps_dec_state->u1_flushfrm == 0))
2984 {
2985 impeg2d_dec_hdr(ps_dec_state,ps_dec_ip ,ps_dec_op);
2986 bytes_remaining -= ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed;
2987 }
2988
2989 if((1 != ps_dec_state->u2_decode_header) && ((bytes_remaining > 0) || ps_dec_state->u1_flushfrm))
2990 {
2991 if(ps_dec_state->u1_flushfrm)
2992 {
2993 if(ps_dec_state->aps_ref_pics[1] != NULL)
2994 {
2995 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[1], ps_dec_state->aps_ref_pics[1]->i4_buf_id);
2996 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF);
2997 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
2998
2999 ps_dec_state->aps_ref_pics[1] = NULL;
3000 ps_dec_state->aps_ref_pics[0] = NULL;
3001
3002 }
3003 else if(ps_dec_state->aps_ref_pics[0] != NULL)
3004 {
3005 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[0], ps_dec_state->aps_ref_pics[0]->i4_buf_id);
3006 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3007
3008 ps_dec_state->aps_ref_pics[0] = NULL;
3009 }
3010 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3011 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3012
3013 ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id);
3014
3015 ps_dec_state->ps_disp_pic = ps_disp_pic;
3016 if(ps_disp_pic == NULL)
3017 {
3018 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3019 }
3020 else
3021 {
3022 WORD32 fmt_conv;
3023 if(0 == ps_dec_state->u4_share_disp_buf)
3024 {
3025 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3026 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3027 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3028 fmt_conv = 1;
3029 }
3030 else
3031 {
3032 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_disp_pic->pu1_y;
3033 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
3034 {
3035 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_disp_pic->pu1_u;
3036 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_disp_pic->pu1_v;
3037 fmt_conv = 0;
3038 }
3039 else
3040 {
3041 UWORD8 *pu1_buf;
3042
3043 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[1];
3044 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = pu1_buf;
3045
3046 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[2];
3047 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = pu1_buf;
3048 fmt_conv = 1;
3049 }
3050 }
3051
3052 if(fmt_conv == 1)
3053 {
3054 impeg2d_format_convert(ps_dec_state, ps_disp_pic,
3055 &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf),
3056 0, ps_dec_state->u2_vertical_size);
3057 }
3058 if(0 == ps_dec_state->u4_share_disp_buf)
3059 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3060
3061 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_ht = ps_dec_state->u2_vertical_size;
3062 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_wd = ps_dec_state->u2_horizontal_size;
3063 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3064
3065 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_disp_pic->i4_buf_id;
3066 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_disp_pic->u4_ts;
3067
3068 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3069
3070 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3071
3072 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3073
3074 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3075 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3076 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3077
3078 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1;
3079 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3080 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1;
3081
3082 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1;
3083 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3084 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1;
3085 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3086
3087 switch(ps_dec_state->i4_chromaFormat)
3088 {
3089 case IV_YUV_420SP_UV:
3090 case IV_YUV_420SP_VU:
3091 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size;
3092 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3093 break;
3094 case IV_YUV_422ILE:
3095 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3096 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3097 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3098 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3099 break;
3100 default:
3101 break;
3102 }
3103
3104
3105 }
3106 if(ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3107 {
3108 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3109 {
3110 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3111 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3112 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3113 ps_dec_state->u4_frm_buf_stride,
3114 ps_dec_state->u2_horizontal_size,
3115 ps_dec_state->u2_vertical_size,
3116 ps_dec_state->i4_chromaFormat,
3117 ps_dec_state->u2_horizontal_size,
3118 ps_dec_state->u2_vertical_size);
3119 }
3120 return(IV_SUCCESS);
3121 }
3122 else
3123 {
3124 ps_dec_state->u1_flushfrm = 0;
3125
3126 return(IV_FAIL);
3127 }
3128
3129 }
3130 else if(ps_dec_state->u1_flushfrm==0)
3131 {
3132 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3133 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3134 if(ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes < 4)
3135 {
3136 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3137 return(IV_FAIL);
3138 }
3139
3140 if(1 == ps_dec_state->u4_share_disp_buf)
3141 {
3142 if(0 == impeg2_buf_mgr_check_free(ps_dec_state->pv_pic_buf_mg))
3143 {
3144 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code =
3145 (IMPEG2D_ERROR_CODES_T)IVD_DEC_REF_BUF_NULL;
3146 return IV_FAIL;
3147 }
3148 }
3149
3150
3151 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3152
3153 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3154
3155 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3156
3157 if (0 == ps_dec_state->u4_frm_buf_stride)
3158 {
3159 ps_dec_state->u4_frm_buf_stride = ALIGN16(ps_dec_state->u2_horizontal_size);
3160 }
3161
3162 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3163 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3164 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3165
3166 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1;
3167 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3168 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1;
3169
3170 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1;
3171 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3172 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1;
3173 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3174
3175 switch(ps_dec_state->i4_chromaFormat)
3176 {
3177 case IV_YUV_420SP_UV:
3178 case IV_YUV_420SP_VU:
3179 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size;
3180 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3181 break;
3182 case IV_YUV_422ILE:
3183 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3184 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3185 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3186 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3187 break;
3188 default:
3189 break;
3190 }
3191
3192 if( ps_dec_state->u1_flushfrm == 0)
3193 {
3194 ps_dec_state->u1_flushcnt = 0;
3195
3196 /*************************************************************************/
3197 /* Frame Decode */
3198 /*************************************************************************/
3199
3200 impeg2d_dec_frm(ps_dec_state,ps_dec_ip,ps_dec_op);
3201
3202 if (IVD_ERROR_NONE ==
3203 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3204 {
3205 if(ps_dec_state->u1_first_frame_done == 0)
3206 {
3207 ps_dec_state->u1_first_frame_done = 1;
3208 }
3209
3210 if(ps_dec_state->ps_disp_pic)
3211 {
3212 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3213 switch(ps_dec_state->ps_disp_pic->e_pic_type)
3214 {
3215 case I_PIC :
3216 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3217 break;
3218
3219 case P_PIC:
3220 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_P_FRAME;
3221 break;
3222
3223 case B_PIC:
3224 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_B_FRAME;
3225 break;
3226
3227 case D_PIC:
3228 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3229 break;
3230
3231 default :
3232 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_FRAMETYPE_DEFAULT;
3233 break;
3234 }
3235 }
3236 else
3237 {
3238 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3239 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_NA_FRAME;
3240 }
3241
3242 ps_dec_state->u4_num_frames_decoded++;
3243 }
3244 }
3245 else
3246 {
3247 ps_dec_state->u1_flushcnt++;
3248 }
3249 }
3250 if(ps_dec_state->ps_disp_pic)
3251 {
3252 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_dec_state->ps_disp_pic->i4_buf_id;
3253 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_dec_state->ps_disp_pic->u4_ts;
3254
3255 if(0 == ps_dec_state->u4_share_disp_buf)
3256 {
3257 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3258 }
3259 }
3260
3261 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3262 {
3263 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3264 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3265 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3266 ps_dec_state->u4_frm_buf_stride,
3267 ps_dec_state->u2_horizontal_size,
3268 ps_dec_state->u2_vertical_size,
3269 ps_dec_state->i4_chromaFormat,
3270 ps_dec_state->u2_horizontal_size,
3271 ps_dec_state->u2_vertical_size);
3272 }
3273
3274 }
3275
3276 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = 1;
3277 ps_dec_op->s_ivd_video_decode_op_t.e4_fld_type = ps_dec_state->s_disp_op.e4_fld_type;
3278
3279
3280 if(ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3281 return IV_FAIL;
3282 else
3283 return IV_SUCCESS;
3284 }
3285