1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements an allocation order for virtual registers.
11 //
12 // The preferred allocation order for a virtual register depends on allocation
13 // hints and target hooks. The AllocationOrder class encapsulates all of that.
14 //
15 //===----------------------------------------------------------------------===//
16
17 #include "AllocationOrder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/RegisterClassInfo.h"
21 #include "llvm/CodeGen/VirtRegMap.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
24
25 using namespace llvm;
26
27 #define DEBUG_TYPE "regalloc"
28
29 // Compare VirtRegMap::getRegAllocPref().
AllocationOrder(unsigned VirtReg,const VirtRegMap & VRM,const RegisterClassInfo & RegClassInfo)30 AllocationOrder::AllocationOrder(unsigned VirtReg,
31 const VirtRegMap &VRM,
32 const RegisterClassInfo &RegClassInfo)
33 : Pos(0) {
34 const MachineFunction &MF = VRM.getMachineFunction();
35 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
38 rewind();
39
40 DEBUG({
41 if (!Hints.empty()) {
42 dbgs() << "hints:";
43 for (unsigned I = 0, E = Hints.size(); I != E; ++I)
44 dbgs() << ' ' << PrintReg(Hints[I], TRI);
45 dbgs() << '\n';
46 }
47 });
48 #ifndef NDEBUG
49 for (unsigned I = 0, E = Hints.size(); I != E; ++I)
50 assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() &&
51 "Target hint is outside allocation order.");
52 #endif
53 }
54