1 //===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the Hexagon target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
18 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
19 
20 #include "HexagonMCTargetDesc.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include <stdint.h>
23 
24 namespace llvm {
25 
26 /// HexagonII - This namespace holds all of the target specific flags that
27 /// instruction info tracks.
28 ///
29 namespace HexagonII {
30   // *** The code below must match HexagonInstrFormat*.td *** //
31 
32   // Insn types.
33   // *** Must match HexagonInstrFormat*.td ***
34   enum Type {
35     TypePSEUDO  = 0,
36     TypeALU32   = 1,
37     TypeCR      = 2,
38     TypeJR      = 3,
39     TypeJ       = 4,
40     TypeLD      = 5,
41     TypeST      = 6,
42     TypeSYSTEM  = 7,
43     TypeXTYPE   = 8,
44     TypeMEMOP   = 9,
45     TypeNV      = 10,
46     TypePREFIX  = 30, // Such as extenders.
47     TypeENDLOOP = 31  // Such as end of a HW loop.
48   };
49 
50   enum SubTarget {
51     HasV2SubT     = 0xf,
52     HasV2SubTOnly = 0x1,
53     NoV2SubT      = 0x0,
54     HasV3SubT     = 0xe,
55     HasV3SubTOnly = 0x2,
56     NoV3SubT      = 0x1,
57     HasV4SubT     = 0xc,
58     NoV4SubT      = 0x3,
59     HasV5SubT     = 0x8,
60     NoV5SubT      = 0x7
61   };
62 
63   enum AddrMode {
64     NoAddrMode     = 0,  // No addressing mode
65     Absolute       = 1,  // Absolute addressing mode
66     AbsoluteSet    = 2,  // Absolute set addressing mode
67     BaseImmOffset  = 3,  // Indirect with offset
68     BaseLongOffset = 4,  // Indirect with long offset
69     BaseRegOffset  = 5,  // Indirect with register offset
70     PostInc        = 6   // Post increment addressing mode
71   };
72 
73   enum MemAccessSize {
74     NoMemAccess = 0,            // Not a memory acces instruction.
75     ByteAccess = 1,             // Byte access instruction (memb).
76     HalfWordAccess = 2,         // Half word access instruction (memh).
77     WordAccess = 3,             // Word access instruction (memw).
78     DoubleWordAccess = 4        // Double word access instruction (memd)
79   };
80 
81   // MCInstrDesc TSFlags
82   // *** Must match HexagonInstrFormat*.td ***
83   enum {
84     // This 5-bit field describes the insn type.
85     TypePos  = 0,
86     TypeMask = 0x1f,
87 
88     // Solo instructions.
89     SoloPos  = 5,
90     SoloMask = 0x1,
91     // Packed only with A or X-type instructions.
92     SoloAXPos  = 6,
93     SoloAXMask = 0x1,
94     // Only A-type instruction in first slot or nothing.
95     SoloAin1Pos  = 7,
96     SoloAin1Mask = 0x1,
97 
98     // Predicated instructions.
99     PredicatedPos  = 8,
100     PredicatedMask = 0x1,
101     PredicatedFalsePos  = 9,
102     PredicatedFalseMask = 0x1,
103     PredicatedNewPos  = 10,
104     PredicatedNewMask = 0x1,
105     PredicateLatePos  = 11,
106     PredicateLateMask = 0x1,
107 
108     // New-Value consumer instructions.
109     NewValuePos  = 12,
110     NewValueMask = 0x1,
111     // New-Value producer instructions.
112     hasNewValuePos  = 13,
113     hasNewValueMask = 0x1,
114     // Which operand consumes or produces a new value.
115     NewValueOpPos  = 14,
116     NewValueOpMask = 0x7,
117     // Stores that can become new-value stores.
118     mayNVStorePos  = 17,
119     mayNVStoreMask = 0x1,
120     // New-value store instructions.
121     NVStorePos  = 18,
122     NVStoreMask = 0x1,
123     // Loads that can become current-value loads.
124     mayCVLoadPos  = 19,
125     mayCVLoadMask = 0x1,
126     // Current-value load instructions.
127     CVLoadPos  = 20,
128     CVLoadMask = 0x1,
129 
130     // Extendable insns.
131     ExtendablePos  = 21,
132     ExtendableMask = 0x1,
133     // Insns must be extended.
134     ExtendedPos  = 22,
135     ExtendedMask = 0x1,
136     // Which operand may be extended.
137     ExtendableOpPos  = 23,
138     ExtendableOpMask = 0x7,
139     // Signed or unsigned range.
140     ExtentSignedPos  = 26,
141     ExtentSignedMask = 0x1,
142     // Number of bits of range before extending operand.
143     ExtentBitsPos  = 27,
144     ExtentBitsMask = 0x1f,
145     // Alignment power-of-two before extending operand.
146     ExtentAlignPos  = 32,
147     ExtentAlignMask = 0x3,
148 
149     // Valid subtargets
150     validSubTargetPos  = 34,
151     validSubTargetMask = 0xf,
152 
153     // Addressing mode for load/store instructions.
154     AddrModePos  = 40,
155     AddrModeMask = 0x7,
156     // Access size for load/store instructions.
157     MemAccessSizePos = 43,
158     MemAccesSizeMask = 0x7,
159 
160     // Branch predicted taken.
161     TakenPos = 47,
162     TakenMask = 0x1,
163 
164     // Floating-point instructions.
165     FPPos  = 48,
166     FPMask = 0x1
167   };
168 
169   // *** The code above must match HexagonInstrFormat*.td *** //
170 
171   // Hexagon specific MO operand flag mask.
172   enum HexagonMOTargetFlagVal {
173     //===------------------------------------------------------------------===//
174     // Hexagon Specific MachineOperand flags.
175     MO_NO_FLAG,
176 
177     HMOTF_ConstExtended = 1,
178 
179     /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
180     /// Used for computing a global address for PIC compilations
181     MO_PCREL,
182 
183     /// MO_GOT - Indicates a GOT-relative relocation
184     MO_GOT,
185 
186     // Low or high part of a symbol.
187     MO_LO16, MO_HI16,
188 
189     // Offset from the base of the SDA.
190     MO_GPREL
191   };
192 
193   enum class InstParseBits : uint32_t {
194     INST_PARSE_MASK       = 0x0000c000,
195     INST_PARSE_PACKET_END = 0x0000c000,
196     INST_PARSE_LOOP_END   = 0x00008000,
197     INST_PARSE_NOT_END    = 0x00004000,
198     INST_PARSE_DUPLEX     = 0x00000000,
199     INST_PARSE_EXTENDER   = 0x00000000
200   };
201 
202 } // End namespace HexagonII.
203 
204 } // End namespace llvm.
205 
206 #endif
207