1//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is the top level entry point for the Mips target.
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18// The overall idea of the PredicateControl class is to chop the Predicates list
19// into subsets that are usually overridden independently. This allows
20// subclasses to partially override the predicates of their superclasses without
21// having to re-add all the existing predicates.
22class PredicateControl {
23  // Predicates for the encoding scheme in use such as HasStdEnc
24  list<Predicate> EncodingPredicates = [];
25  // Predicates for the GPR size such as IsGP64bit
26  list<Predicate> GPRPredicates = [];
27  // Predicates for the FGR size and layout such as IsFP64bit
28  list<Predicate> FGRPredicates = [];
29  // Predicates for the instruction group membership such as ISA's and ASE's
30  list<Predicate> InsnPredicates = [];
31  // Predicates for anything else
32  list<Predicate> AdditionalPredicates = [];
33  list<Predicate> Predicates = !listconcat(EncodingPredicates,
34                                           GPRPredicates,
35                                           FGRPredicates,
36                                           InsnPredicates,
37                                           AdditionalPredicates);
38}
39
40// Like Requires<> but for the AdditionalPredicates list
41class AdditionalRequires<list<Predicate> preds> {
42  list<Predicate> AdditionalPredicates = preds;
43}
44
45//===----------------------------------------------------------------------===//
46// Register File, Calling Conv, Instruction Descriptions
47//===----------------------------------------------------------------------===//
48
49include "MipsRegisterInfo.td"
50include "MipsSchedule.td"
51include "MipsInstrInfo.td"
52include "MipsCallingConv.td"
53
54def MipsInstrInfo : InstrInfo;
55
56//===----------------------------------------------------------------------===//
57// Mips Subtarget features                                                    //
58//===----------------------------------------------------------------------===//
59
60def FeatureNoABICalls  : SubtargetFeature<"noabicalls", "NoABICalls", "true",
61                                "Disable SVR4-style position-independent code">;
62def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
63                                "General Purpose Registers are 64-bit wide">;
64def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
65                                "Support 64-bit FP registers">;
66def FeatureFPXX        : SubtargetFeature<"fpxx", "IsFPXX", "true",
67                                "Support for FPXX">;
68def FeatureNaN2008     : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
69                                "IEEE 754-2008 NaN encoding">;
70def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
71                                "true", "Only supports single precision float">;
72def FeatureNoOddSPReg  : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
73                              "Disable odd numbered single-precision "
74                              "registers">;
75def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
76                                "true", "Enable vector FPU instructions">;
77def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
78                                "Mips I ISA Support [highly experimental]">;
79def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
80                                "Mips II ISA Support [highly experimental]",
81                                [FeatureMips1]>;
82def FeatureMips3_32    : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
83                                "Subset of MIPS-III that is also in MIPS32 "
84                                "[highly experimental]">;
85def FeatureMips3_32r2  : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
86                                "Subset of MIPS-III that is also in MIPS32r2 "
87                                "[highly experimental]">;
88def FeatureMips3       : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
89                                "MIPS III ISA Support [highly experimental]",
90                                [FeatureMips2, FeatureMips3_32,
91                                 FeatureMips3_32r2, FeatureGP64Bit,
92                                 FeatureFP64Bit]>;
93def FeatureMips4_32    : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
94                                "Subset of MIPS-IV that is also in MIPS32 "
95                                "[highly experimental]">;
96def FeatureMips4_32r2  : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
97                                "Subset of MIPS-IV that is also in MIPS32r2 "
98                                "[highly experimental]">;
99def FeatureMips4       : SubtargetFeature<"mips4", "MipsArchVersion",
100                                "Mips4", "MIPS IV ISA Support",
101                                [FeatureMips3, FeatureMips4_32,
102                                 FeatureMips4_32r2]>;
103def FeatureMips5_32r2  : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
104                                "Subset of MIPS-V that is also in MIPS32r2 "
105                                "[highly experimental]">;
106def FeatureMips5       : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
107                                "MIPS V ISA Support [highly experimental]",
108                                [FeatureMips4, FeatureMips5_32r2]>;
109def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
110                                "Mips32 ISA Support",
111                                [FeatureMips2, FeatureMips3_32,
112                                 FeatureMips4_32]>;
113def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
114                                "Mips32r2", "Mips32r2 ISA Support",
115                                [FeatureMips3_32r2, FeatureMips4_32r2,
116                                 FeatureMips5_32r2, FeatureMips32]>;
117def FeatureMips32r3    : SubtargetFeature<"mips32r3", "MipsArchVersion",
118                                "Mips32r3", "Mips32r3 ISA Support",
119                                [FeatureMips32r2]>;
120def FeatureMips32r5    : SubtargetFeature<"mips32r5", "MipsArchVersion",
121                                "Mips32r5", "Mips32r5 ISA Support",
122                                [FeatureMips32r3]>;
123def FeatureMips32r6    : SubtargetFeature<"mips32r6", "MipsArchVersion",
124                                "Mips32r6",
125                                "Mips32r6 ISA Support [experimental]",
126                                [FeatureMips32r5, FeatureFP64Bit,
127                                 FeatureNaN2008]>;
128def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
129                                "Mips64", "Mips64 ISA Support",
130                                [FeatureMips5, FeatureMips32]>;
131def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
132                                "Mips64r2", "Mips64r2 ISA Support",
133                                [FeatureMips64, FeatureMips32r2]>;
134def FeatureMips64r3    : SubtargetFeature<"mips64r3", "MipsArchVersion",
135                                "Mips64r3", "Mips64r3 ISA Support",
136                                [FeatureMips64r2, FeatureMips32r3]>;
137def FeatureMips64r5    : SubtargetFeature<"mips64r5", "MipsArchVersion",
138                                "Mips64r5", "Mips64r5 ISA Support",
139                                [FeatureMips64r3, FeatureMips32r5]>;
140def FeatureMips64r6    : SubtargetFeature<"mips64r6", "MipsArchVersion",
141                                "Mips64r6",
142                                "Mips64r6 ISA Support [experimental]",
143                                [FeatureMips32r6, FeatureMips64r5,
144                                 FeatureNaN2008]>;
145
146def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
147                                      "Mips16 mode">;
148
149def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
150def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
151                                    "Mips DSP-R2 ASE", [FeatureDSP]>;
152
153def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
154
155def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
156                                         "microMips mode">;
157
158def FeatureCnMips     : SubtargetFeature<"cnmips", "HasCnMips",
159                                "true", "Octeon cnMIPS Support",
160                                [FeatureMips64r2]>;
161
162//===----------------------------------------------------------------------===//
163// Mips processors supported.
164//===----------------------------------------------------------------------===//
165
166class Proc<string Name, list<SubtargetFeature> Features>
167 : Processor<Name, MipsGenericItineraries, Features>;
168
169def : Proc<"mips1", [FeatureMips1]>;
170def : Proc<"mips2", [FeatureMips2]>;
171def : Proc<"mips32", [FeatureMips32]>;
172def : Proc<"mips32r2", [FeatureMips32r2]>;
173def : Proc<"mips32r3", [FeatureMips32r3]>;
174def : Proc<"mips32r5", [FeatureMips32r5]>;
175def : Proc<"mips32r6", [FeatureMips32r6]>;
176
177def : Proc<"mips3", [FeatureMips3]>;
178def : Proc<"mips4", [FeatureMips4]>;
179def : Proc<"mips5", [FeatureMips5]>;
180def : Proc<"mips64", [FeatureMips64]>;
181def : Proc<"mips64r2", [FeatureMips64r2]>;
182def : Proc<"mips64r3", [FeatureMips64r3]>;
183def : Proc<"mips64r5", [FeatureMips64r5]>;
184def : Proc<"mips64r6", [FeatureMips64r6]>;
185def : Proc<"mips16", [FeatureMips16]>;
186def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
187
188def MipsAsmParser : AsmParser {
189  let ShouldEmitMatchRegisterName = 0;
190  let MnemonicContainsDot = 1;
191}
192
193def MipsAsmParserVariant : AsmParserVariant {
194  int Variant = 0;
195
196  // Recognize hard coded registers.
197  string RegisterPrefix = "$";
198}
199
200def Mips : Target {
201  let InstructionSet = MipsInstrInfo;
202  let AssemblyParsers = [MipsAsmParser];
203  let AssemblyParserVariants = [MipsAsmParserVariant];
204}
205