1//===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Tablegen register definitions common to all hw codegen targets. 11// 12//===----------------------------------------------------------------------===// 13 14let Namespace = "AMDGPU" in { 15 16foreach Index = 0-15 in { 17 // Indices are used in a variety of ways here, so don't set a size/offset. 18 def sub#Index : SubRegIndex<-1, -1>; 19} 20 21def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">; 22 23} 24 25include "R600RegisterInfo.td" 26include "SIRegisterInfo.td" 27