1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief This file provides AMDGPU specific target descriptions.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "AMDGPUMCTargetDesc.h"
16 #include "AMDGPUMCAsmInfo.h"
17 #include "InstPrinter/AMDGPUInstPrinter.h"
18 #include "SIDefines.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MachineLocation.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
28
29 using namespace llvm;
30
31 #define GET_INSTRINFO_MC_DESC
32 #include "AMDGPUGenInstrInfo.inc"
33
34 #define GET_SUBTARGETINFO_MC_DESC
35 #include "AMDGPUGenSubtargetInfo.inc"
36
37 #define GET_REGINFO_MC_DESC
38 #include "AMDGPUGenRegisterInfo.inc"
39
createAMDGPUMCInstrInfo()40 static MCInstrInfo *createAMDGPUMCInstrInfo() {
41 MCInstrInfo *X = new MCInstrInfo();
42 InitAMDGPUMCInstrInfo(X);
43 return X;
44 }
45
createAMDGPUMCRegisterInfo(StringRef TT)46 static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
47 MCRegisterInfo *X = new MCRegisterInfo();
48 InitAMDGPUMCRegisterInfo(X, 0);
49 return X;
50 }
51
createAMDGPUMCSubtargetInfo(StringRef TT,StringRef CPU,StringRef FS)52 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
53 StringRef FS) {
54 MCSubtargetInfo * X = new MCSubtargetInfo();
55 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
56 return X;
57 }
58
createAMDGPUMCCodeGenInfo(StringRef TT,Reloc::Model RM,CodeModel::Model CM,CodeGenOpt::Level OL)59 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
60 CodeModel::Model CM,
61 CodeGenOpt::Level OL) {
62 MCCodeGenInfo *X = new MCCodeGenInfo();
63 X->InitMCCodeGenInfo(RM, CM, OL);
64 return X;
65 }
66
createAMDGPUMCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)67 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
68 unsigned SyntaxVariant,
69 const MCAsmInfo &MAI,
70 const MCInstrInfo &MII,
71 const MCRegisterInfo &MRI) {
72 return new AMDGPUInstPrinter(MAI, MII, MRI);
73 }
74
LLVMInitializeR600TargetMC()75 extern "C" void LLVMInitializeR600TargetMC() {
76 for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) {
77 RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
78
79 TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo);
80 TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
81 TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
82 TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
83 TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
84 TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
85 }
86
87 TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget,
88 createR600MCCodeEmitter);
89 TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createSIMCCodeEmitter);
90 }
91