1//===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes XOP (eXtended OPerations)
11//
12//===----------------------------------------------------------------------===//
13
14multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
15  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
16           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
17           [(set VR128:$dst, (Int VR128:$src))]>, XOP;
18  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
19           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
20           [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
21}
22
23let ExeDomain = SSEPackedInt in {
24  defm VPHSUBWD  : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, loadv2i64>;
25  defm VPHSUBDQ  : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, loadv2i64>;
26  defm VPHSUBBW  : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, loadv2i64>;
27  defm VPHADDWQ  : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, loadv2i64>;
28  defm VPHADDWD  : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, loadv2i64>;
29  defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, loadv2i64>;
30  defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, loadv2i64>;
31  defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, loadv2i64>;
32  defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, loadv2i64>;
33  defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, loadv2i64>;
34  defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, loadv2i64>;
35  defm VPHADDDQ  : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, loadv2i64>;
36  defm VPHADDBW  : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, loadv2i64>;
37  defm VPHADDBQ  : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, loadv2i64>;
38  defm VPHADDBD  : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, loadv2i64>;
39}
40
41// Scalar load 2 addr operand instructions
42multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
43                     Operand memop, ComplexPattern mem_cpat> {
44  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
45           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
46           [(set VR128:$dst, (Int VR128:$src))]>, XOP;
47  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
48           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
49           [(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP;
50}
51
52multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
53                     PatFrag memop> {
54  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
55           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
56           [(set VR128:$dst, (Int VR128:$src))]>, XOP;
57  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
58           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
59           [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
60}
61
62multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
63                     PatFrag memop> {
64  def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
65           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
66           [(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L;
67  def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
68           !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
69           [(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L;
70}
71
72let ExeDomain = SSEPackedSingle in {
73  defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
74                           ssmem, sse_load_f32>;
75  defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, loadv4f32>;
76  defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256, loadv8f32>;
77}
78
79let ExeDomain = SSEPackedDouble in {
80  defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
81                           sdmem, sse_load_f64>;
82  defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, loadv2f64>;
83  defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256, loadv4f64>;
84}
85
86multiclass xop3op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
87  def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
88           (ins VR128:$src1, VR128:$src2),
89           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
90           [(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, XOP_4VOp3;
91  def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
92           (ins VR128:$src1, i128mem:$src2),
93           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
94           [(set VR128:$dst,
95              (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2))))]>,
96           XOP_4V, VEX_W;
97  def mr : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
98           (ins i128mem:$src1, VR128:$src2),
99           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
100           [(set VR128:$dst,
101              (Int (bitconvert (loadv2i64 addr:$src1)), VR128:$src2))]>,
102             XOP_4VOp3;
103}
104
105let ExeDomain = SSEPackedInt in {
106  defm VPSHLW : xop3op<0x95, "vpshlw", int_x86_xop_vpshlw>;
107  defm VPSHLQ : xop3op<0x97, "vpshlq", int_x86_xop_vpshlq>;
108  defm VPSHLD : xop3op<0x96, "vpshld", int_x86_xop_vpshld>;
109  defm VPSHLB : xop3op<0x94, "vpshlb", int_x86_xop_vpshlb>;
110  defm VPSHAW : xop3op<0x99, "vpshaw", int_x86_xop_vpshaw>;
111  defm VPSHAQ : xop3op<0x9B, "vpshaq", int_x86_xop_vpshaq>;
112  defm VPSHAD : xop3op<0x9A, "vpshad", int_x86_xop_vpshad>;
113  defm VPSHAB : xop3op<0x98, "vpshab", int_x86_xop_vpshab>;
114  defm VPROTW : xop3op<0x91, "vprotw", int_x86_xop_vprotw>;
115  defm VPROTQ : xop3op<0x93, "vprotq", int_x86_xop_vprotq>;
116  defm VPROTD : xop3op<0x92, "vprotd", int_x86_xop_vprotd>;
117  defm VPROTB : xop3op<0x90, "vprotb", int_x86_xop_vprotb>;
118}
119
120multiclass xop3opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> {
121  def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
122           (ins VR128:$src1, i8imm:$src2),
123           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
124           [(set VR128:$dst, (Int VR128:$src1, imm:$src2))]>, XOP;
125  def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
126           (ins i128mem:$src1, i8imm:$src2),
127           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
128           [(set VR128:$dst,
129             (Int (bitconvert (loadv2i64 addr:$src1)), imm:$src2))]>, XOP;
130}
131
132let ExeDomain = SSEPackedInt in {
133  defm VPROTW : xop3opimm<0xC1, "vprotw", int_x86_xop_vprotwi>;
134  defm VPROTQ : xop3opimm<0xC3, "vprotq", int_x86_xop_vprotqi>;
135  defm VPROTD : xop3opimm<0xC2, "vprotd", int_x86_xop_vprotdi>;
136  defm VPROTB : xop3opimm<0xC0, "vprotb", int_x86_xop_vprotbi>;
137}
138
139// Instruction where second source can be memory, but third must be register
140multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> {
141  let isCommutable = 1 in
142  def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
143           (ins VR128:$src1, VR128:$src2, VR128:$src3),
144           !strconcat(OpcodeStr,
145           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
146           [(set VR128:$dst,
147              (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V, VEX_I8IMM;
148  def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
149           (ins VR128:$src1, i128mem:$src2, VR128:$src3),
150           !strconcat(OpcodeStr,
151           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
152           [(set VR128:$dst,
153              (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
154              VR128:$src3))]>, XOP_4V, VEX_I8IMM;
155}
156
157let ExeDomain = SSEPackedInt in {
158  defm VPMADCSWD  : xop4opm2<0xB6, "vpmadcswd", int_x86_xop_vpmadcswd>;
159  defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", int_x86_xop_vpmadcsswd>;
160  defm VPMACSWW   : xop4opm2<0x95, "vpmacsww", int_x86_xop_vpmacsww>;
161  defm VPMACSWD   : xop4opm2<0x96, "vpmacswd", int_x86_xop_vpmacswd>;
162  defm VPMACSSWW  : xop4opm2<0x85, "vpmacssww", int_x86_xop_vpmacssww>;
163  defm VPMACSSWD  : xop4opm2<0x86, "vpmacsswd", int_x86_xop_vpmacsswd>;
164  defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", int_x86_xop_vpmacssdql>;
165  defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", int_x86_xop_vpmacssdqh>;
166  defm VPMACSSDD  : xop4opm2<0x8E, "vpmacssdd", int_x86_xop_vpmacssdd>;
167  defm VPMACSDQL  : xop4opm2<0x97, "vpmacsdql", int_x86_xop_vpmacsdql>;
168  defm VPMACSDQH  : xop4opm2<0x9F, "vpmacsdqh", int_x86_xop_vpmacsdqh>;
169  defm VPMACSDD   : xop4opm2<0x9E, "vpmacsdd", int_x86_xop_vpmacsdd>;
170}
171
172// Instruction where second source can be memory, third must be imm8
173multiclass xopvpcom<bits<8> opc, string Suffix, Intrinsic Int> {
174  let isCommutable = 1 in
175  def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
176           (ins VR128:$src1, VR128:$src2, XOPCC:$cc),
177           !strconcat("vpcom${cc}", Suffix,
178           "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
179           [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, i8immZExt3:$cc))]>,
180           XOP_4V;
181  def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
182           (ins VR128:$src1, i128mem:$src2, XOPCC:$cc),
183           !strconcat("vpcom${cc}", Suffix,
184           "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
185           [(set VR128:$dst,
186             (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
187              i8immZExt3:$cc))]>, XOP_4V;
188  let isAsmParserOnly = 1, hasSideEffects = 0 in {
189    def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
190                 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
191                 !strconcat("vpcom", Suffix,
192                 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
193                 []>, XOP_4V;
194    let mayLoad = 1 in
195    def mi_alt : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
196                 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
197                 !strconcat("vpcom", Suffix,
198                 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
199                 []>, XOP_4V;
200  }
201}
202
203let ExeDomain = SSEPackedInt in { // SSE integer instructions
204  defm VPCOMB  : xopvpcom<0xCC, "b", int_x86_xop_vpcomb>;
205  defm VPCOMW  : xopvpcom<0xCD, "w", int_x86_xop_vpcomw>;
206  defm VPCOMD  : xopvpcom<0xCE, "d", int_x86_xop_vpcomd>;
207  defm VPCOMQ  : xopvpcom<0xCF, "q", int_x86_xop_vpcomq>;
208  defm VPCOMUB : xopvpcom<0xEC, "ub", int_x86_xop_vpcomub>;
209  defm VPCOMUW : xopvpcom<0xED, "uw", int_x86_xop_vpcomuw>;
210  defm VPCOMUD : xopvpcom<0xEE, "ud", int_x86_xop_vpcomud>;
211  defm VPCOMUQ : xopvpcom<0xEF, "uq", int_x86_xop_vpcomuq>;
212}
213
214// Instruction where either second or third source can be memory
215multiclass xop4op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
216  def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
217           (ins VR128:$src1, VR128:$src2, VR128:$src3),
218           !strconcat(OpcodeStr,
219           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
220           [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, VR128:$src3))]>,
221           XOP_4V, VEX_I8IMM;
222  def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
223           (ins VR128:$src1, VR128:$src2, i128mem:$src3),
224           !strconcat(OpcodeStr,
225           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
226           [(set VR128:$dst,
227             (Int VR128:$src1, VR128:$src2,
228              (bitconvert (loadv2i64 addr:$src3))))]>,
229           XOP_4V, VEX_I8IMM, VEX_W, MemOp4;
230  def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
231           (ins VR128:$src1, i128mem:$src2, VR128:$src3),
232           !strconcat(OpcodeStr,
233           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
234           [(set VR128:$dst,
235             (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
236              VR128:$src3))]>,
237           XOP_4V, VEX_I8IMM;
238}
239
240let ExeDomain = SSEPackedInt in {
241  defm VPPERM : xop4op<0xA3, "vpperm", int_x86_xop_vpperm>;
242  defm VPCMOV : xop4op<0xA2, "vpcmov", int_x86_xop_vpcmov>;
243}
244
245multiclass xop4op256<bits<8> opc, string OpcodeStr, Intrinsic Int> {
246  def rrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
247           (ins VR256:$src1, VR256:$src2, VR256:$src3),
248           !strconcat(OpcodeStr,
249           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
250           [(set VR256:$dst, (Int VR256:$src1, VR256:$src2, VR256:$src3))]>,
251           XOP_4V, VEX_I8IMM, VEX_L;
252  def rmY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
253           (ins VR256:$src1, VR256:$src2, i256mem:$src3),
254           !strconcat(OpcodeStr,
255           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
256           [(set VR256:$dst,
257             (Int VR256:$src1, VR256:$src2,
258              (bitconvert (loadv4i64 addr:$src3))))]>,
259           XOP_4V, VEX_I8IMM, VEX_W, MemOp4, VEX_L;
260  def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
261           (ins VR256:$src1, f256mem:$src2, VR256:$src3),
262           !strconcat(OpcodeStr,
263           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
264           [(set VR256:$dst,
265             (Int VR256:$src1, (bitconvert (loadv4i64 addr:$src2)),
266              VR256:$src3))]>,
267           XOP_4V, VEX_I8IMM, VEX_L;
268}
269
270let ExeDomain = SSEPackedInt in
271  defm VPCMOV : xop4op256<0xA2, "vpcmov", int_x86_xop_vpcmov_256>;
272
273multiclass xop5op<bits<8> opc, string OpcodeStr, Intrinsic Int128,
274                  Intrinsic Int256, PatFrag ld_128, PatFrag ld_256> {
275  def rr : IXOP5<opc, MRMSrcReg, (outs VR128:$dst),
276        (ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4),
277        !strconcat(OpcodeStr,
278        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
279        [(set VR128:$dst,
280           (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
281  def rm : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
282        (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
283        !strconcat(OpcodeStr,
284        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
285        [(set VR128:$dst,
286           (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
287        VEX_W, MemOp4;
288  def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
289        (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
290        !strconcat(OpcodeStr,
291        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
292        [(set VR128:$dst,
293           (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
294  def rrY : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
295        (ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4),
296        !strconcat(OpcodeStr,
297        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
298        [(set VR256:$dst,
299          (Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>, VEX_L;
300  def rmY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
301        (ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
302        !strconcat(OpcodeStr,
303        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
304        [(set VR256:$dst,
305          (Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>,
306        VEX_W, MemOp4, VEX_L;
307  def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
308        (ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
309        !strconcat(OpcodeStr,
310        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
311        [(set VR256:$dst,
312           (Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>,
313        VEX_L;
314}
315
316let ExeDomain = SSEPackedDouble in
317  defm VPERMIL2PD : xop5op<0x49, "vpermil2pd", int_x86_xop_vpermil2pd,
318                           int_x86_xop_vpermil2pd_256, loadv2f64, loadv4f64>;
319
320let ExeDomain = SSEPackedSingle in
321  defm VPERMIL2PS : xop5op<0x48, "vpermil2ps", int_x86_xop_vpermil2ps,
322                           int_x86_xop_vpermil2ps_256, loadv4f32, loadv8f32>;
323
324