1; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
2
3define i32 @qadds(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
4; CHECK-LABEL: qadds:
5; CHECK: sqadd s0, s0, s1
6  %vecext = extractelement <4 x i32> %b, i32 0
7  %vecext1 = extractelement <4 x i32> %c, i32 0
8  %vqadd.i = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind
9  ret i32 %vqadd.i
10}
11
12define i64 @qaddd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
13; CHECK-LABEL: qaddd:
14; CHECK: sqadd d0, d0, d1
15  %vecext = extractelement <2 x i64> %b, i32 0
16  %vecext1 = extractelement <2 x i64> %c, i32 0
17  %vqadd.i = tail call i64 @llvm.aarch64.neon.sqadd.i64(i64 %vecext, i64 %vecext1) nounwind
18  ret i64 %vqadd.i
19}
20
21define i32 @uqadds(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
22; CHECK-LABEL: uqadds:
23; CHECK: uqadd s0, s0, s1
24  %vecext = extractelement <4 x i32> %b, i32 0
25  %vecext1 = extractelement <4 x i32> %c, i32 0
26  %vqadd.i = tail call i32 @llvm.aarch64.neon.uqadd.i32(i32 %vecext, i32 %vecext1) nounwind
27  ret i32 %vqadd.i
28}
29
30define i64 @uqaddd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
31; CHECK-LABEL: uqaddd:
32; CHECK: uqadd d0, d0, d1
33  %vecext = extractelement <2 x i64> %b, i32 0
34  %vecext1 = extractelement <2 x i64> %c, i32 0
35  %vqadd.i = tail call i64 @llvm.aarch64.neon.uqadd.i64(i64 %vecext, i64 %vecext1) nounwind
36  ret i64 %vqadd.i
37}
38
39declare i64 @llvm.aarch64.neon.uqadd.i64(i64, i64) nounwind readnone
40declare i32 @llvm.aarch64.neon.uqadd.i32(i32, i32) nounwind readnone
41declare i64 @llvm.aarch64.neon.sqadd.i64(i64, i64) nounwind readnone
42declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32) nounwind readnone
43
44define i32 @qsubs(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
45; CHECK-LABEL: qsubs:
46; CHECK: sqsub s0, s0, s1
47  %vecext = extractelement <4 x i32> %b, i32 0
48  %vecext1 = extractelement <4 x i32> %c, i32 0
49  %vqsub.i = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 %vecext, i32 %vecext1) nounwind
50  ret i32 %vqsub.i
51}
52
53define i64 @qsubd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
54; CHECK-LABEL: qsubd:
55; CHECK: sqsub d0, d0, d1
56  %vecext = extractelement <2 x i64> %b, i32 0
57  %vecext1 = extractelement <2 x i64> %c, i32 0
58  %vqsub.i = tail call i64 @llvm.aarch64.neon.sqsub.i64(i64 %vecext, i64 %vecext1) nounwind
59  ret i64 %vqsub.i
60}
61
62define i32 @uqsubs(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
63; CHECK-LABEL: uqsubs:
64; CHECK: uqsub s0, s0, s1
65  %vecext = extractelement <4 x i32> %b, i32 0
66  %vecext1 = extractelement <4 x i32> %c, i32 0
67  %vqsub.i = tail call i32 @llvm.aarch64.neon.uqsub.i32(i32 %vecext, i32 %vecext1) nounwind
68  ret i32 %vqsub.i
69}
70
71define i64 @uqsubd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
72; CHECK-LABEL: uqsubd:
73; CHECK: uqsub d0, d0, d1
74  %vecext = extractelement <2 x i64> %b, i32 0
75  %vecext1 = extractelement <2 x i64> %c, i32 0
76  %vqsub.i = tail call i64 @llvm.aarch64.neon.uqsub.i64(i64 %vecext, i64 %vecext1) nounwind
77  ret i64 %vqsub.i
78}
79
80declare i64 @llvm.aarch64.neon.uqsub.i64(i64, i64) nounwind readnone
81declare i32 @llvm.aarch64.neon.uqsub.i32(i32, i32) nounwind readnone
82declare i64 @llvm.aarch64.neon.sqsub.i64(i64, i64) nounwind readnone
83declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32) nounwind readnone
84
85define i32 @qabss(<4 x i32> %b, <4 x i32> %c) nounwind readnone {
86; CHECK-LABEL: qabss:
87; CHECK: sqabs s0, s0
88; CHECK: ret
89  %vecext = extractelement <4 x i32> %b, i32 0
90  %vqabs.i = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %vecext) nounwind
91  ret i32 %vqabs.i
92}
93
94define i64 @qabsd(<2 x i64> %b, <2 x i64> %c) nounwind readnone {
95; CHECK-LABEL: qabsd:
96; CHECK: sqabs d0, d0
97; CHECK: ret
98  %vecext = extractelement <2 x i64> %b, i32 0
99  %vqabs.i = tail call i64 @llvm.aarch64.neon.sqabs.i64(i64 %vecext) nounwind
100  ret i64 %vqabs.i
101}
102
103define i32 @qnegs(<4 x i32> %b, <4 x i32> %c) nounwind readnone {
104; CHECK-LABEL: qnegs:
105; CHECK: sqneg s0, s0
106; CHECK: ret
107  %vecext = extractelement <4 x i32> %b, i32 0
108  %vqneg.i = tail call i32 @llvm.aarch64.neon.sqneg.i32(i32 %vecext) nounwind
109  ret i32 %vqneg.i
110}
111
112define i64 @qnegd(<2 x i64> %b, <2 x i64> %c) nounwind readnone {
113; CHECK-LABEL: qnegd:
114; CHECK: sqneg d0, d0
115; CHECK: ret
116  %vecext = extractelement <2 x i64> %b, i32 0
117  %vqneg.i = tail call i64 @llvm.aarch64.neon.sqneg.i64(i64 %vecext) nounwind
118  ret i64 %vqneg.i
119}
120
121declare i64 @llvm.aarch64.neon.sqneg.i64(i64) nounwind readnone
122declare i32 @llvm.aarch64.neon.sqneg.i32(i32) nounwind readnone
123declare i64 @llvm.aarch64.neon.sqabs.i64(i64) nounwind readnone
124declare i32 @llvm.aarch64.neon.sqabs.i32(i32) nounwind readnone
125
126
127define i32 @vqmovund(<2 x i64> %b) nounwind readnone {
128; CHECK-LABEL: vqmovund:
129; CHECK: sqxtun s0, d0
130  %vecext = extractelement <2 x i64> %b, i32 0
131  %vqmovun.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtun.i32.i64(i64 %vecext) nounwind
132  ret i32 %vqmovun.i
133}
134
135define i32 @vqmovnd_s(<2 x i64> %b) nounwind readnone {
136; CHECK-LABEL: vqmovnd_s:
137; CHECK: sqxtn s0, d0
138  %vecext = extractelement <2 x i64> %b, i32 0
139  %vqmovn.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64 %vecext) nounwind
140  ret i32 %vqmovn.i
141}
142
143define i32 @vqmovnd_u(<2 x i64> %b) nounwind readnone {
144; CHECK-LABEL: vqmovnd_u:
145; CHECK: uqxtn s0, d0
146  %vecext = extractelement <2 x i64> %b, i32 0
147  %vqmovn.i = tail call i32 @llvm.aarch64.neon.scalar.uqxtn.i32.i64(i64 %vecext) nounwind
148  ret i32 %vqmovn.i
149}
150
151declare i32 @llvm.aarch64.neon.scalar.uqxtn.i32.i64(i64) nounwind readnone
152declare i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64) nounwind readnone
153declare i32 @llvm.aarch64.neon.scalar.sqxtun.i32.i64(i64) nounwind readnone
154