1; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
2
3define i128 @shl(i128 %r, i128 %s) nounwind readnone {
4; CHECK-LABEL: shl:
5; CHECK: lsl  [[XREG_0:x[0-9]+]], x1, x2
6; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
7; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
8; CHECK-NEXT: lsr  [[XREG_3:x[0-9]+]], x0, [[XREG_2]]
9; CHECK-NEXT: orr [[XREG_6:x[0-9]+]], [[XREG_3]], [[XREG_0]]
10; CHECK-NEXT: sub [[XREG_4:x[0-9]+]], x2, #64
11; CHECK-NEXT: lsl  [[XREG_5:x[0-9]+]], x0, [[XREG_4]]
12; CHECK-NEXT: cmp   [[XREG_4]], #0
13; CHECK-NEXT: csel  x1, [[XREG_5]], [[XREG_6]], ge
14; CHECK-NEXT: lsl  [[SMALLSHIFT_LO:x[0-9]+]], x0, x2
15; CHECK-NEXT: csel  x0, xzr, [[SMALLSHIFT_LO]], ge
16; CHECK-NEXT: ret
17
18  %shl = shl i128 %r, %s
19  ret i128 %shl
20}
21
22define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
23; CHECK-LABEL: ashr:
24; CHECK: lsr  [[XREG_0:x[0-9]+]], x0, x2
25; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
26; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
27; CHECK-NEXT: lsl  [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
28; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
29; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
30; CHECK-NEXT: asr  [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
31; CHECK-NEXT: cmp   [[XREG_5]], #0
32; CHECK-NEXT: csel  x0, [[XREG_6]], [[XREG_4]], ge
33; CHECK-NEXT: asr  [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
34; CHECK-NEXT: asr [[BIGSHIFT_HI:x[0-9]+]], x1, #63
35; CHECK-NEXT: csel x1, [[BIGSHIFT_HI]], [[SMALLSHIFT_HI]], ge
36; CHECK-NEXT: ret
37
38  %shr = ashr i128 %r, %s
39  ret i128 %shr
40}
41
42define i128 @lshr(i128 %r, i128 %s) nounwind readnone {
43; CHECK-LABEL: lshr:
44; CHECK: lsr  [[XREG_0:x[0-9]+]], x0, x2
45; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
46; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
47; CHECK-NEXT: lsl  [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
48; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
49; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
50; CHECK-NEXT: lsr  [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
51; CHECK-NEXT: cmp   [[XREG_5]], #0
52; CHECK-NEXT: csel  x0, [[XREG_6]], [[XREG_4]], ge
53; CHECK-NEXT: lsr  [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
54; CHECK-NEXT: csel x1, xzr, [[SMALLSHIFT_HI]], ge
55; CHECK-NEXT: ret
56
57  %shr = lshr i128 %r, %s
58  ret i128 %shr
59}
60