1; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
2; rdar://13214163 - Make sure we generate a correct lookup table for the TBL
3; instruction when the element size of the vector is not 8 bits. We were
4; getting both the endianness wrong and the element indexing wrong.
5define <8 x i16> @foo(<8 x i16> %a) nounwind readnone {
6; CHECK:	.section	__TEXT,__literal16,16byte_literals
7; CHECK:	.align	4
8; CHECK:lCPI0_0:
9; CHECK:	.byte	0                       ; 0x0
10; CHECK:	.byte	1                       ; 0x1
11; CHECK:	.byte	0                       ; 0x0
12; CHECK:	.byte	1                       ; 0x1
13; CHECK:	.byte	0                       ; 0x0
14; CHECK:	.byte	1                       ; 0x1
15; CHECK:	.byte	0                       ; 0x0
16; CHECK:	.byte	1                       ; 0x1
17; CHECK:	.byte	8                       ; 0x8
18; CHECK:	.byte	9                       ; 0x9
19; CHECK:	.byte	8                       ; 0x8
20; CHECK:	.byte	9                       ; 0x9
21; CHECK:	.byte	8                       ; 0x8
22; CHECK:	.byte	9                       ; 0x9
23; CHECK:	.byte	8                       ; 0x8
24; CHECK:	.byte	9                       ; 0x9
25; CHECK:	.section __TEXT,__text,regular,pure_instructions
26; CHECK:	.globl	_foo
27; CHECK:	.align	2
28; CHECK:_foo:                                   ; @foo
29; CHECK:	adrp	[[BASE:x[0-9]+]], lCPI0_0@PAGE
30; CHECK:	ldr	q[[REG:[0-9]+]], {{\[}}[[BASE]], lCPI0_0@PAGEOFF]
31; CHECK:	tbl.16b	v0, { v0 }, v[[REG]]
32; CHECK:	ret
33
34  %val = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4>
35  ret <8 x i16> %val
36}
37