1; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s 2; RUN: llc < %s -mtriple=thumbv7-apple-darwin > %t 3; RUN: FileCheck %s < %t 4; RUN: FileCheck %s < %t --check-prefix=CHECK-T2ADDRMODE 5 6%0 = type { i32, i32 } 7 8; CHECK-LABEL: f0: 9; CHECK: ldrexd 10define i64 @f0(i8* %p) nounwind readonly { 11entry: 12 %ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p) 13 %0 = extractvalue %0 %ldrexd, 1 14 %1 = extractvalue %0 %ldrexd, 0 15 %2 = zext i32 %0 to i64 16 %3 = zext i32 %1 to i64 17 %shl = shl nuw i64 %2, 32 18 %4 = or i64 %shl, %3 19 ret i64 %4 20} 21 22; CHECK-LABEL: f1: 23; CHECK: strexd 24define i32 @f1(i8* %ptr, i64 %val) nounwind { 25entry: 26 %tmp4 = trunc i64 %val to i32 27 %tmp6 = lshr i64 %val, 32 28 %tmp7 = trunc i64 %tmp6 to i32 29 %strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, i8* %ptr) 30 ret i32 %strexd 31} 32 33declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly 34declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind 35 36; CHECK-LABEL: test_load_i8: 37; CHECK: ldrexb r0, [r0] 38; CHECK-NOT: uxtb 39; CHECK-NOT: and 40define zeroext i8 @test_load_i8(i8* %addr) { 41 %val = call i32 @llvm.arm.ldrex.p0i8(i8* %addr) 42 %val8 = trunc i32 %val to i8 43 ret i8 %val8 44} 45 46; CHECK-LABEL: test_load_i16: 47; CHECK: ldrexh r0, [r0] 48; CHECK-NOT: uxth 49; CHECK-NOT: and 50define zeroext i16 @test_load_i16(i16* %addr) { 51 %val = call i32 @llvm.arm.ldrex.p0i16(i16* %addr) 52 %val16 = trunc i32 %val to i16 53 ret i16 %val16 54} 55 56; CHECK-LABEL: test_load_i32: 57; CHECK: ldrex r0, [r0] 58define i32 @test_load_i32(i32* %addr) { 59 %val = call i32 @llvm.arm.ldrex.p0i32(i32* %addr) 60 ret i32 %val 61} 62 63declare i32 @llvm.arm.ldrex.p0i8(i8*) nounwind readonly 64declare i32 @llvm.arm.ldrex.p0i16(i16*) nounwind readonly 65declare i32 @llvm.arm.ldrex.p0i32(i32*) nounwind readonly 66 67; CHECK-LABEL: test_store_i8: 68; CHECK-NOT: uxtb 69; CHECK: strexb r0, r1, [r2] 70define i32 @test_store_i8(i32, i8 %val, i8* %addr) { 71 %extval = zext i8 %val to i32 72 %res = call i32 @llvm.arm.strex.p0i8(i32 %extval, i8* %addr) 73 ret i32 %res 74} 75 76; CHECK-LABEL: test_store_i16: 77; CHECK-NOT: uxth 78; CHECK: strexh r0, r1, [r2] 79define i32 @test_store_i16(i32, i16 %val, i16* %addr) { 80 %extval = zext i16 %val to i32 81 %res = call i32 @llvm.arm.strex.p0i16(i32 %extval, i16* %addr) 82 ret i32 %res 83} 84 85; CHECK-LABEL: test_store_i32: 86; CHECK: strex r0, r1, [r2] 87define i32 @test_store_i32(i32, i32 %val, i32* %addr) { 88 %res = call i32 @llvm.arm.strex.p0i32(i32 %val, i32* %addr) 89 ret i32 %res 90} 91 92declare i32 @llvm.arm.strex.p0i8(i32, i8*) nounwind 93declare i32 @llvm.arm.strex.p0i16(i32, i16*) nounwind 94declare i32 @llvm.arm.strex.p0i32(i32, i32*) nounwind 95 96; CHECK-LABEL: test_clear: 97; CHECK: clrex 98define void @test_clear() { 99 call void @llvm.arm.clrex() 100 ret void 101} 102 103declare void @llvm.arm.clrex() nounwind 104 105@base = global i32* null 106 107define void @excl_addrmode() { 108; CHECK-T2ADDRMODE-LABEL: excl_addrmode: 109 %base1020 = load i32*, i32** @base 110 %offset1020 = getelementptr i32, i32* %base1020, i32 255 111 call i32 @llvm.arm.ldrex.p0i32(i32* %offset1020) 112 call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1020) 113; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [{{r[0-9]+}}, #1020] 114; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}, #1020] 115 116 %base1024 = load i32*, i32** @base 117 %offset1024 = getelementptr i32, i32* %base1024, i32 256 118 call i32 @llvm.arm.ldrex.p0i32(i32* %offset1024) 119 call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1024) 120; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], {{r[0-9]+}}, #1024 121; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] 122; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] 123 124 %base1 = load i32*, i32** @base 125 %addr8 = bitcast i32* %base1 to i8* 126 %offset1_8 = getelementptr i8, i8* %addr8, i32 1 127 %offset1 = bitcast i8* %offset1_8 to i32* 128 call i32 @llvm.arm.ldrex.p0i32(i32* %offset1) 129 call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1) 130; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #1 131; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] 132; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] 133 134 %local = alloca i8, i32 1024 135 %local32 = bitcast i8* %local to i32* 136 call i32 @llvm.arm.ldrex.p0i32(i32* %local32) 137 call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32) 138; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp 139; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] 140; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] 141 142 ret void 143} 144 145; LLVM should know, even across basic blocks, that ldrex is setting the high 146; bits of its i32 to 0. There should be no zero-extend operation. 147define zeroext i8 @test_cross_block_zext_i8(i1 %tst, i8* %addr) { 148; CHECK: test_cross_block_zext_i8: 149; CHECK-NOT: uxtb 150; CHECK-NOT: and 151; CHECK: bx lr 152 %val = call i32 @llvm.arm.ldrex.p0i8(i8* %addr) 153 br i1 %tst, label %end, label %mid 154mid: 155 ret i8 42 156end: 157 %val8 = trunc i32 %val to i8 158 ret i8 %val8 159} 160