1; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
2
3; ARM & AArch64 run an extra SimplifyCFG which disrupts this test.
4; XFAIL: arm,aarch64
5
6; Make sure we have the correct weight attached to each successor.
7define i32 @test2(i32 %x) nounwind uwtable readnone ssp {
8; CHECK: Machine code for function test2:
9entry:
10  %conv = sext i32 %x to i64
11  switch i64 %conv, label %return [
12    i64 0, label %sw.bb
13    i64 1, label %sw.bb
14    i64 4, label %sw.bb
15    i64 5, label %sw.bb1
16  ], !prof !0
17; CHECK: BB#0: derived from LLVM BB %entry
18; CHECK: Successors according to CFG: BB#2(64) BB#4(14)
19; CHECK: BB#4: derived from LLVM BB %entry
20; CHECK: Successors according to CFG: BB#1(10) BB#5(4)
21; CHECK: BB#5: derived from LLVM BB %entry
22; CHECK: Successors according to CFG: BB#1(4) BB#3(7)
23
24sw.bb:
25  br label %return
26
27sw.bb1:
28  br label %return
29
30return:
31  %retval.0 = phi i32 [ 5, %sw.bb1 ], [ 1, %sw.bb ], [ 0, %entry ]
32  ret i32 %retval.0
33}
34
35!0 = !{!"branch_weights", i32 7, i32 6, i32 4, i32 4, i32 64}
36