1; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
2
3target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
4
5
6define void @one(i64 %a, i64 %b, i64* %p1, i64* %p2) {
7; CHECK: cvt.s64.s8
8; CHECK: cvt.s64.s8
9entry:
10  %sext = shl i64 %a, 56
11  %conv1 = ashr exact i64 %sext, 56
12  %sext1 = shl i64 %b, 56
13  %conv4 = ashr exact i64 %sext1, 56
14  %shr = ashr i64 %a, 16
15  %shr9 = ashr i64 %b, 16
16  %add = add nsw i64 %conv4, %conv1
17  store i64 %add, i64* %p1, align 8
18  %add17 = add nsw i64 %shr9, %shr
19  store i64 %add17, i64* %p2, align 8
20  ret void
21}
22
23
24define void @two(i64 %a, i64 %b, i64* %p1, i64* %p2) {
25entry:
26; CHECK: cvt.s64.s32
27; CHECK: cvt.s64.s32
28  %sext = shl i64 %a, 32
29  %conv1 = ashr exact i64 %sext, 32
30  %sext1 = shl i64 %b, 32
31  %conv4 = ashr exact i64 %sext1, 32
32  %shr = ashr i64 %a, 16
33  %shr9 = ashr i64 %b, 16
34  %add = add nsw i64 %conv4, %conv1
35  store i64 %add, i64* %p1, align 8
36  %add17 = add nsw i64 %shr9, %shr
37  store i64 %add17, i64* %p2, align 8
38  ret void
39}
40
41
42define void @three(i64 %a, i64 %b, i64* %p1, i64* %p2) {
43entry:
44; CHECK: cvt.s64.s16
45; CHECK: cvt.s64.s16
46  %sext = shl i64 %a, 48
47  %conv1 = ashr exact i64 %sext, 48
48  %sext1 = shl i64 %b, 48
49  %conv4 = ashr exact i64 %sext1, 48
50  %shr = ashr i64 %a, 16
51  %shr9 = ashr i64 %b, 16
52  %add = add nsw i64 %conv4, %conv1
53  store i64 %add, i64* %p1, align 8
54  %add17 = add nsw i64 %shr9, %shr
55  store i64 %add17, i64* %p2, align 8
56  ret void
57}
58
59
60define void @four(i32 %a, i32 %b, i32* %p1, i32* %p2) {
61entry:
62; CHECK: cvt.s32.s8
63; CHECK: cvt.s32.s8
64  %sext = shl i32 %a, 24
65  %conv1 = ashr exact i32 %sext, 24
66  %sext1 = shl i32 %b, 24
67  %conv4 = ashr exact i32 %sext1, 24
68  %shr = ashr i32 %a, 16
69  %shr9 = ashr i32 %b, 16
70  %add = add nsw i32 %conv4, %conv1
71  store i32 %add, i32* %p1, align 4
72  %add17 = add nsw i32 %shr9, %shr
73  store i32 %add17, i32* %p2, align 4
74  ret void
75}
76
77
78define void @five(i32 %a, i32 %b, i32* %p1, i32* %p2) {
79entry:
80; CHECK: cvt.s32.s16
81; CHECK: cvt.s32.s16
82  %sext = shl i32 %a, 16
83  %conv1 = ashr exact i32 %sext, 16
84  %sext1 = shl i32 %b, 16
85  %conv4 = ashr exact i32 %sext1, 16
86  %shr = ashr i32 %a, 16
87  %shr9 = ashr i32 %b, 16
88  %add = add nsw i32 %conv4, %conv1
89  store i32 %add, i32* %p1, align 4
90  %add17 = add nsw i32 %shr9, %shr
91  store i32 %add17, i32* %p2, align 4
92  ret void
93}
94
95
96define void @six(i16 %a, i16 %b, i16* %p1, i16* %p2) {
97entry:
98; CHECK: cvt.s16.s8
99; CHECK: cvt.s16.s8
100  %sext = shl i16 %a, 8
101  %conv1 = ashr exact i16 %sext, 8
102  %sext1 = shl i16 %b, 8
103  %conv4 = ashr exact i16 %sext1, 8
104  %shr = ashr i16 %a, 8
105  %shr9 = ashr i16 %b, 8
106  %add = add nsw i16 %conv4, %conv1
107  store i16 %add, i16* %p1, align 4
108  %add17 = add nsw i16 %shr9, %shr
109  store i16 %add17, i16* %p2, align 4
110  ret void
111}
112