1; RUN: llc -mcpu=pwr7 < %s | FileCheck %s 2target datalayout = "E-m:e-i64:64-n32:64" 3target triple = "powerpc64-unknown-linux-gnu" 4 5define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 { 6entry: 7 %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0 8 %1 = and i8 %0, 1 9 %tobool3 = icmp ne i8 %1, 0 10 ret i1 %tobool3 11 12; CHECK-LABEL: @testi1 13; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 14; CHECK-DAG: li [[REG1:[0-9]+]], 0 15; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1 16; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 17; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1 18; CHECK-DAG: li [[REG4:[0-9]+]], 1 19; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]] 20; CHECK: blr 21} 22 23define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 { 24entry: 25 %0 = tail call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) #0 26 ret i32 %0 27 28; The ABI sign_extend should combine with the any_extend from the asm result, 29; and the result will be 0 or -1. This highlights the fact that only the first 30; bit is meaningful. 31; CHECK-LABEL: @testi32 32; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 33; CHECK-DAG: li [[REG1:[0-9]+]], 0 34; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1 35; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 36; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1 37; CHECK-DAG: li [[REG4:[0-9]+]], -1 38; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]] 39; CHECK: blr 40} 41 42define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 { 43entry: 44 %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2) #0 45 ret i8 %0 46 47; CHECK-LABEL: @testi8 48; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 49; CHECK-DAG: li [[REG1:[0-9]+]], 0 50; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1 51; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 52; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1 53; CHECK-DAG: li [[REG4:[0-9]+]], 1 54; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]] 55; CHECK: blr 56} 57 58attributes #0 = { nounwind } 59 60