1; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
2; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
3
4; Function Attrs: nounwind
5define zeroext i8 @_Z6testcff(float %arg) {
6entry:
7  %arg.addr = alloca float, align 4
8  store float %arg, float* %arg.addr, align 4
9  %0 = load float, float* %arg.addr, align 4
10  %conv = fptoui float %0 to i8
11  ret i8 %conv
12; CHECK-LABEL: @_Z6testcff
13; CHECK: xscvdpsxws [[CONVREG01:[0-9]+]], 1
14; CHECK: mfvsrwz 3, [[CONVREG01]]
15}
16
17; Function Attrs: nounwind
18define float @_Z6testfcc(i8 zeroext %arg) {
19entry:
20  %arg.addr = alloca i8, align 1
21  store i8 %arg, i8* %arg.addr, align 1
22  %0 = load i8, i8* %arg.addr, align 1
23  %conv = uitofp i8 %0 to float
24  ret float %conv
25; CHECK-LABEL: @_Z6testfcc
26; CHECK: mtvsrwz [[MOVEREG01:[0-9]+]], 3
27; FIXME: Once we have XSCVUXDSP implemented, this will change
28; CHECK: fcfidus 1, [[MOVEREG01]]
29}
30
31; Function Attrs: nounwind
32define zeroext i8 @_Z6testcdd(double %arg) {
33entry:
34  %arg.addr = alloca double, align 8
35  store double %arg, double* %arg.addr, align 8
36  %0 = load double, double* %arg.addr, align 8
37  %conv = fptoui double %0 to i8
38  ret i8 %conv
39; CHECK-LABEL: @_Z6testcdd
40; CHECK: xscvdpsxws [[CONVREG02:[0-9]+]], 1
41; CHECK: mfvsrwz 3, [[CONVREG02]]
42}
43
44; Function Attrs: nounwind
45define double @_Z6testdcc(i8 zeroext %arg) {
46entry:
47  %arg.addr = alloca i8, align 1
48  store i8 %arg, i8* %arg.addr, align 1
49  %0 = load i8, i8* %arg.addr, align 1
50  %conv = uitofp i8 %0 to double
51  ret double %conv
52; CHECK-LABEL: @_Z6testdcc
53; CHECK: mtvsrwz [[MOVEREG02:[0-9]+]], 3
54; CHECK: xscvuxddp 1, [[MOVEREG02]]
55}
56
57; Function Attrs: nounwind
58define zeroext i8 @_Z7testucff(float %arg) {
59entry:
60  %arg.addr = alloca float, align 4
61  store float %arg, float* %arg.addr, align 4
62  %0 = load float, float* %arg.addr, align 4
63  %conv = fptoui float %0 to i8
64  ret i8 %conv
65; CHECK-LABEL: @_Z7testucff
66; CHECK: xscvdpsxws [[CONVREG03:[0-9]+]], 1
67; CHECK: mfvsrwz 3, [[CONVREG03]]
68}
69
70; Function Attrs: nounwind
71define float @_Z7testfuch(i8 zeroext %arg) {
72entry:
73  %arg.addr = alloca i8, align 1
74  store i8 %arg, i8* %arg.addr, align 1
75  %0 = load i8, i8* %arg.addr, align 1
76  %conv = uitofp i8 %0 to float
77  ret float %conv
78; CHECK-LABEL: @_Z7testfuch
79; CHECK: mtvsrwz [[MOVEREG03:[0-9]+]], 3
80; FIXME: Once we have XSCVUXDSP implemented, this will change
81; CHECK: fcfidus 1, [[MOVEREG03]]
82}
83
84; Function Attrs: nounwind
85define zeroext i8 @_Z7testucdd(double %arg) {
86entry:
87  %arg.addr = alloca double, align 8
88  store double %arg, double* %arg.addr, align 8
89  %0 = load double, double* %arg.addr, align 8
90  %conv = fptoui double %0 to i8
91  ret i8 %conv
92; CHECK-LABEL: @_Z7testucdd
93; CHECK: xscvdpsxws [[CONVREG04:[0-9]+]], 1
94; CHECK: mfvsrwz 3, [[CONVREG04]]
95}
96
97; Function Attrs: nounwind
98define double @_Z7testduch(i8 zeroext %arg) {
99entry:
100  %arg.addr = alloca i8, align 1
101  store i8 %arg, i8* %arg.addr, align 1
102  %0 = load i8, i8* %arg.addr, align 1
103  %conv = uitofp i8 %0 to double
104  ret double %conv
105; CHECK-LABEL: @_Z7testduch
106; CHECK: mtvsrwz [[MOVEREG04:[0-9]+]], 3
107; CHECK: xscvuxddp 1, [[MOVEREG04]]
108}
109
110; Function Attrs: nounwind
111define signext i16 @_Z6testsff(float %arg) {
112entry:
113  %arg.addr = alloca float, align 4
114  store float %arg, float* %arg.addr, align 4
115  %0 = load float, float* %arg.addr, align 4
116  %conv = fptosi float %0 to i16
117  ret i16 %conv
118; CHECK-LABEL: @_Z6testsff
119; CHECK: xscvdpsxws [[CONVREG05:[0-9]+]], 1
120; CHECK: mfvsrwz 3, [[CONVREG05]]
121}
122
123; Function Attrs: nounwind
124define float @_Z6testfss(i16 signext %arg) {
125entry:
126  %arg.addr = alloca i16, align 2
127  store i16 %arg, i16* %arg.addr, align 2
128  %0 = load i16, i16* %arg.addr, align 2
129  %conv = sitofp i16 %0 to float
130  ret float %conv
131; CHECK-LABEL: @_Z6testfss
132; CHECK: mtvsrwa [[MOVEREG05:[0-9]+]], 3
133; FIXME: Once we have XSCVSXDSP implemented, this will change
134; CHECK: fcfids 1, [[MOVEREG05]]
135}
136
137; Function Attrs: nounwind
138define signext i16 @_Z6testsdd(double %arg) {
139entry:
140  %arg.addr = alloca double, align 8
141  store double %arg, double* %arg.addr, align 8
142  %0 = load double, double* %arg.addr, align 8
143  %conv = fptosi double %0 to i16
144  ret i16 %conv
145; CHECK-LABEL: @_Z6testsdd
146; CHECK: xscvdpsxws [[CONVREG06:[0-9]+]], 1
147; CHECK: mfvsrwz 3, [[CONVREG06]]
148}
149
150; Function Attrs: nounwind
151define double @_Z6testdss(i16 signext %arg) {
152entry:
153  %arg.addr = alloca i16, align 2
154  store i16 %arg, i16* %arg.addr, align 2
155  %0 = load i16, i16* %arg.addr, align 2
156  %conv = sitofp i16 %0 to double
157  ret double %conv
158; CHECK-LABEL: @_Z6testdss
159; CHECK: mtvsrwa [[MOVEREG06:[0-9]+]], 3
160; CHECK: xscvsxddp 1, [[MOVEREG06]]
161}
162
163; Function Attrs: nounwind
164define zeroext i16 @_Z7testusff(float %arg) {
165entry:
166  %arg.addr = alloca float, align 4
167  store float %arg, float* %arg.addr, align 4
168  %0 = load float, float* %arg.addr, align 4
169  %conv = fptoui float %0 to i16
170  ret i16 %conv
171; CHECK-LABEL: @_Z7testusff
172; CHECK: xscvdpsxws [[CONVREG07:[0-9]+]], 1
173; CHECK: mfvsrwz 3, [[CONVREG07]]
174}
175
176; Function Attrs: nounwind
177define float @_Z7testfust(i16 zeroext %arg) {
178entry:
179  %arg.addr = alloca i16, align 2
180  store i16 %arg, i16* %arg.addr, align 2
181  %0 = load i16, i16* %arg.addr, align 2
182  %conv = uitofp i16 %0 to float
183  ret float %conv
184; CHECK-LABEL: @_Z7testfust
185; CHECK: mtvsrwz [[MOVEREG07:[0-9]+]], 3
186; FIXME: Once we have XSCVUXDSP implemented, this will change
187; CHECK: fcfidus 1, [[MOVEREG07]]
188}
189
190; Function Attrs: nounwind
191define zeroext i16 @_Z7testusdd(double %arg) {
192entry:
193  %arg.addr = alloca double, align 8
194  store double %arg, double* %arg.addr, align 8
195  %0 = load double, double* %arg.addr, align 8
196  %conv = fptoui double %0 to i16
197  ret i16 %conv
198; CHECK-LABEL: @_Z7testusdd
199; CHECK: xscvdpsxws [[CONVREG08:[0-9]+]], 1
200; CHECK: mfvsrwz 3, [[CONVREG08]]
201}
202
203; Function Attrs: nounwind
204define double @_Z7testdust(i16 zeroext %arg) {
205entry:
206  %arg.addr = alloca i16, align 2
207  store i16 %arg, i16* %arg.addr, align 2
208  %0 = load i16, i16* %arg.addr, align 2
209  %conv = uitofp i16 %0 to double
210  ret double %conv
211; CHECK-LABEL: @_Z7testdust
212; CHECK: mtvsrwz [[MOVEREG08:[0-9]+]], 3
213; CHECK: xscvuxddp 1, [[MOVEREG08]]
214}
215
216; Function Attrs: nounwind
217define signext i32 @_Z6testiff(float %arg) {
218entry:
219  %arg.addr = alloca float, align 4
220  store float %arg, float* %arg.addr, align 4
221  %0 = load float, float* %arg.addr, align 4
222  %conv = fptosi float %0 to i32
223  ret i32 %conv
224; CHECK-LABEL: @_Z6testiff
225; CHECK: xscvdpsxws [[CONVREG09:[0-9]+]], 1
226; CHECK: mfvsrwz 3, [[CONVREG09]]
227}
228
229; Function Attrs: nounwind
230define float @_Z6testfii(i32 signext %arg) {
231entry:
232  %arg.addr = alloca i32, align 4
233  store i32 %arg, i32* %arg.addr, align 4
234  %0 = load i32, i32* %arg.addr, align 4
235  %conv = sitofp i32 %0 to float
236  ret float %conv
237; CHECK-LABEL: @_Z6testfii
238; CHECK: mtvsrwa [[MOVEREG09:[0-9]+]], 3
239; FIXME: Once we have XSCVSXDSP implemented, this will change
240; CHECK: fcfids 1, [[MOVEREG09]]
241}
242
243; Function Attrs: nounwind
244define signext i32 @_Z6testidd(double %arg) {
245entry:
246  %arg.addr = alloca double, align 8
247  store double %arg, double* %arg.addr, align 8
248  %0 = load double, double* %arg.addr, align 8
249  %conv = fptosi double %0 to i32
250  ret i32 %conv
251; CHECK-LABEL: @_Z6testidd
252; CHECK: xscvdpsxws [[CONVREG10:[0-9]+]], 1
253; CHECK: mfvsrwz 3, [[CONVREG10]]
254}
255
256; Function Attrs: nounwind
257define double @_Z6testdii(i32 signext %arg) {
258entry:
259  %arg.addr = alloca i32, align 4
260  store i32 %arg, i32* %arg.addr, align 4
261  %0 = load i32, i32* %arg.addr, align 4
262  %conv = sitofp i32 %0 to double
263  ret double %conv
264; CHECK-LABEL: @_Z6testdii
265; CHECK: mtvsrwa [[MOVEREG10:[0-9]+]], 3
266; CHECK: xscvsxddp 1, [[MOVEREG10]]
267}
268
269; Function Attrs: nounwind
270define zeroext i32 @_Z7testuiff(float %arg) {
271entry:
272  %arg.addr = alloca float, align 4
273  store float %arg, float* %arg.addr, align 4
274  %0 = load float, float* %arg.addr, align 4
275  %conv = fptoui float %0 to i32
276  ret i32 %conv
277; CHECK-LABEL: @_Z7testuiff
278; CHECK: xscvdpuxws [[CONVREG11:[0-9]+]], 1
279; CHECK: mfvsrwz 3, [[CONVREG11]]
280}
281
282; Function Attrs: nounwind
283define float @_Z7testfuij(i32 zeroext %arg) {
284entry:
285  %arg.addr = alloca i32, align 4
286  store i32 %arg, i32* %arg.addr, align 4
287  %0 = load i32, i32* %arg.addr, align 4
288  %conv = uitofp i32 %0 to float
289  ret float %conv
290; CHECK-LABEL: @_Z7testfuij
291; CHECK: mtvsrwz [[MOVEREG11:[0-9]+]], 3
292; FIXME: Once we have XSCVUXDSP implemented, this will change
293; CHECK: fcfidus 1, [[MOVEREG11]]
294}
295
296; Function Attrs: nounwind
297define zeroext i32 @_Z7testuidd(double %arg) {
298entry:
299  %arg.addr = alloca double, align 8
300  store double %arg, double* %arg.addr, align 8
301  %0 = load double, double* %arg.addr, align 8
302  %conv = fptoui double %0 to i32
303  ret i32 %conv
304; CHECK-LABEL: @_Z7testuidd
305; CHECK: xscvdpuxws [[CONVREG12:[0-9]+]], 1
306; CHECK: mfvsrwz 3, [[CONVREG12]]
307}
308
309; Function Attrs: nounwind
310define double @_Z7testduij(i32 zeroext %arg) {
311entry:
312  %arg.addr = alloca i32, align 4
313  store i32 %arg, i32* %arg.addr, align 4
314  %0 = load i32, i32* %arg.addr, align 4
315  %conv = uitofp i32 %0 to double
316  ret double %conv
317; CHECK-LABEL: @_Z7testduij
318; CHECK: mtvsrwz [[MOVEREG12:[0-9]+]], 3
319; CHECK: xscvuxddp 1, [[MOVEREG12]]
320}
321
322; Function Attrs: nounwind
323define i64 @_Z7testllff(float %arg) {
324entry:
325  %arg.addr = alloca float, align 4
326  store float %arg, float* %arg.addr, align 4
327  %0 = load float, float* %arg.addr, align 4
328  %conv = fptosi float %0 to i64
329  ret i64 %conv
330; CHECK-LABEL: @_Z7testllff
331; CHECK: xscvdpsxds [[CONVREG13:[0-9]+]], 1
332; CHECK: mfvsrd 3, [[CONVREG13]]
333}
334
335; Function Attrs: nounwind
336define float @_Z7testfllx(i64 %arg) {
337entry:
338  %arg.addr = alloca i64, align 8
339  store i64 %arg, i64* %arg.addr, align 8
340  %0 = load i64, i64* %arg.addr, align 8
341  %conv = sitofp i64 %0 to float
342  ret float %conv
343; CHECK-LABEL:@_Z7testfllx
344; CHECK: mtvsrd [[MOVEREG13:[0-9]+]], 3
345; FIXME: Once we have XSCVSXDSP implemented, this will change
346; CHECK: fcfids 1, [[MOVEREG13]]
347}
348
349; Function Attrs: nounwind
350define i64 @_Z7testlldd(double %arg) {
351entry:
352  %arg.addr = alloca double, align 8
353  store double %arg, double* %arg.addr, align 8
354  %0 = load double, double* %arg.addr, align 8
355  %conv = fptosi double %0 to i64
356  ret i64 %conv
357; CHECK-LABEL: @_Z7testlldd
358; CHECK: xscvdpsxds [[CONVREG14:[0-9]+]], 1
359; CHECK: mfvsrd 3, [[CONVREG14]]
360}
361
362; Function Attrs: nounwind
363define double @_Z7testdllx(i64 %arg) {
364entry:
365  %arg.addr = alloca i64, align 8
366  store i64 %arg, i64* %arg.addr, align 8
367  %0 = load i64, i64* %arg.addr, align 8
368  %conv = sitofp i64 %0 to double
369  ret double %conv
370; CHECK-LABEL: @_Z7testdllx
371; CHECK: mtvsrd [[MOVEREG14:[0-9]+]], 3
372; CHECK: xscvsxddp 1, [[MOVEREG14]]
373}
374
375; Function Attrs: nounwind
376define i64 @_Z8testullff(float %arg) {
377entry:
378  %arg.addr = alloca float, align 4
379  store float %arg, float* %arg.addr, align 4
380  %0 = load float, float* %arg.addr, align 4
381  %conv = fptoui float %0 to i64
382  ret i64 %conv
383; CHECK-LABEL: @_Z8testullff
384; CHECK: xscvdpuxds [[CONVREG15:[0-9]+]], 1
385; CHECK: mfvsrd 3, [[CONVREG15]]
386}
387
388; Function Attrs: nounwind
389define float @_Z8testfully(i64 %arg) {
390entry:
391  %arg.addr = alloca i64, align 8
392  store i64 %arg, i64* %arg.addr, align 8
393  %0 = load i64, i64* %arg.addr, align 8
394  %conv = uitofp i64 %0 to float
395  ret float %conv
396; CHECK-LABEL: @_Z8testfully
397; CHECK: mtvsrd [[MOVEREG15:[0-9]+]], 3
398; FIXME: Once we have XSCVUXDSP implemented, this will change
399; CHECK: fcfidus 1, [[MOVEREG15]]
400}
401
402; Function Attrs: nounwind
403define i64 @_Z8testulldd(double %arg) {
404entry:
405  %arg.addr = alloca double, align 8
406  store double %arg, double* %arg.addr, align 8
407  %0 = load double, double* %arg.addr, align 8
408  %conv = fptoui double %0 to i64
409  ret i64 %conv
410; CHECK-LABEL: @_Z8testulldd
411; CHECK: xscvdpuxds [[CONVREG16:[0-9]+]], 1
412; CHECK: mfvsrd 3, [[CONVREG16]]
413}
414
415; Function Attrs: nounwind
416define double @_Z8testdully(i64 %arg) {
417entry:
418  %arg.addr = alloca i64, align 8
419  store i64 %arg, i64* %arg.addr, align 8
420  %0 = load i64, i64* %arg.addr, align 8
421  %conv = uitofp i64 %0 to double
422  ret double %conv
423; CHECK-LABEL: @_Z8testdully
424; CHECK: mtvsrd [[MOVEREG16:[0-9]+]], 3
425; CHECK: xscvuxddp 1, [[MOVEREG16]]
426}
427