1; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s
2target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
3target triple = "powerpc64-unknown-linux-gnu"
4
5define signext i32 @foo(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 {
6entry:
7  %sub = sub nsw i32 %a, %b
8  store i32 %sub, i32* %c, align 4
9  %cmp = icmp sgt i32 %a, %b
10  %cond = select i1 %cmp, i32 %a, i32 %b
11  ret i32 %cond
12
13; CHECK: @foo
14; CHECK-NOT: subf.
15}
16
17define signext i32 @foo2(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 {
18entry:
19  %shl = shl i32 %a, %b
20  store i32 %shl, i32* %c, align 4
21  %cmp = icmp sgt i32 %shl, 0
22  %conv = zext i1 %cmp to i32
23  ret i32 %conv
24
25; CHECK: @foo2
26; CHECK-NOT: slw.
27}
28
29define i64 @fool(i64 %a, i64 %b, i64* nocapture %c) #0 {
30entry:
31  %sub = sub nsw i64 %a, %b
32  store i64 %sub, i64* %c, align 8
33  %cmp = icmp sgt i64 %a, %b
34  %cond = select i1 %cmp, i64 %a, i64 %b
35  ret i64 %cond
36
37; CHECK: @fool
38; CHECK: subf. [[REG:[0-9]+]], 4, 3
39; CHECK: isel 3, 3, 4, 1
40; CHECK: std [[REG]], 0(5)
41}
42
43define i64 @foolb(i64 %a, i64 %b, i64* nocapture %c) #0 {
44entry:
45  %sub = sub nsw i64 %a, %b
46  store i64 %sub, i64* %c, align 8
47  %cmp = icmp sle i64 %a, %b
48  %cond = select i1 %cmp, i64 %a, i64 %b
49  ret i64 %cond
50
51; CHECK: @foolb
52; CHECK: subf. [[REG:[0-9]+]], 4, 3
53; CHECK: isel 3, 4, 3, 1
54; CHECK: std [[REG]], 0(5)
55}
56
57define i64 @foolc(i64 %a, i64 %b, i64* nocapture %c) #0 {
58entry:
59  %sub = sub nsw i64 %b, %a
60  store i64 %sub, i64* %c, align 8
61  %cmp = icmp sgt i64 %a, %b
62  %cond = select i1 %cmp, i64 %a, i64 %b
63  ret i64 %cond
64
65; CHECK: @foolc
66; CHECK: subf. [[REG:[0-9]+]], 3, 4
67; CHECK: isel 3, 3, 4, 0
68; CHECK: std [[REG]], 0(5)
69}
70
71define i64 @foold(i64 %a, i64 %b, i64* nocapture %c) #0 {
72entry:
73  %sub = sub nsw i64 %b, %a
74  store i64 %sub, i64* %c, align 8
75  %cmp = icmp eq i64 %a, %b
76  %cond = select i1 %cmp, i64 %a, i64 %b
77  ret i64 %cond
78
79; CHECK: @foold
80; CHECK: subf. [[REG:[0-9]+]], 3, 4
81; CHECK: isel 3, 3, 4, 2
82; CHECK: std [[REG]], 0(5)
83}
84
85define i64 @foold2(i64 %a, i64 %b, i64* nocapture %c) #0 {
86entry:
87  %sub = sub nsw i64 %a, %b
88  store i64 %sub, i64* %c, align 8
89  %cmp = icmp eq i64 %a, %b
90  %cond = select i1 %cmp, i64 %a, i64 %b
91  ret i64 %cond
92
93; CHECK: @foold2
94; CHECK: subf. [[REG:[0-9]+]], 4, 3
95; CHECK: isel 3, 3, 4, 2
96; CHECK: std [[REG]], 0(5)
97}
98
99define i64 @foo2l(i64 %a, i64 %b, i64* nocapture %c) #0 {
100entry:
101  %shl = shl i64 %a, %b
102  store i64 %shl, i64* %c, align 8
103  %cmp = icmp sgt i64 %shl, 0
104  %conv1 = zext i1 %cmp to i64
105  ret i64 %conv1
106
107; CHECK: @foo2l
108; CHECK: sld. 4, 3, 4
109; CHECK: std 4, 0(5)
110}
111
112define double @food(double %a, double %b, double* nocapture %c) #0 {
113entry:
114  %sub = fsub double %a, %b
115  store double %sub, double* %c, align 8
116  %cmp = fcmp ogt double %a, %b
117  %cond = select i1 %cmp, double %a, double %b
118  ret double %cond
119
120; CHECK: @food
121; CHECK-NOT: fsub. 0, 1, 2
122; CHECK: stfd 0, 0(5)
123}
124
125define float @foof(float %a, float %b, float* nocapture %c) #0 {
126entry:
127  %sub = fsub float %a, %b
128  store float %sub, float* %c, align 4
129  %cmp = fcmp ogt float %a, %b
130  %cond = select i1 %cmp, float %a, float %b
131  ret float %cond
132
133; CHECK: @foof
134; CHECK-NOT: fsubs. 0, 1, 2
135; CHECK: stfs 0, 0(5)
136}
137
138declare i64 @llvm.ctpop.i64(i64);
139
140define signext i64 @fooct(i64 signext %a, i64 signext %b, i64* nocapture %c) #0 {
141entry:
142  %sub = sub nsw i64 %a, %b
143  %subc = call i64 @llvm.ctpop.i64(i64 %sub)
144  store i64 %subc, i64* %c, align 4
145  %cmp = icmp sgt i64 %subc, 0
146  %cond = select i1 %cmp, i64 %a, i64 %b
147  ret i64 %cond
148
149; CHECK: @fooct
150; CHECK-NOT: popcntd.
151}
152
153