1; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s 2target triple = "powerpc64-bgq-linux" 3 4@Q = constant <4 x i1> <i1 0, i1 undef, i1 1, i1 1>, align 16 5@R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16 6 7define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x i1> %c) nounwind readnone { 8entry: 9 %r = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 10 ret <4 x float> %r 11 12; CHECK-LABEL: @test1 13; CHECK: qvfsel 1, 3, 1, 2 14; CHECK: blr 15} 16 17define <4 x float> @test2(<4 x float> %a, <4 x float> %b, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind readnone { 18entry: 19 %v = insertelement <4 x i1> undef, i1 %c1, i32 0 20 %v2 = insertelement <4 x i1> %v, i1 %c2, i32 1 21 %v3 = insertelement <4 x i1> %v2, i1 %c3, i32 2 22 %v4 = insertelement <4 x i1> %v3, i1 %c4, i32 3 23 %r = select <4 x i1> %v4, <4 x float> %a, <4 x float> %b 24 ret <4 x float> %r 25 26; CHECK-LABEL: @test2 27; CHECK: stw 28; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]], 29; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], 30; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]] 31; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]] 32; CHECK: qvfsel 1, [[REG4]], 1, 2 33; CHECK: blr 34} 35 36define <4 x i1> @test3(<4 x i1> %a) nounwind readnone { 37entry: 38 %v = and <4 x i1> %a, <i1 0, i1 undef, i1 1, i1 1> 39 ret <4 x i1> %v 40 41; CHECK-LABEL: @test3 42; CHECK: qvlfsx [[REG:[0-9]+]], 43; qvflogical 1, 1, [[REG]], 1 44; blr 45} 46 47define <4 x i1> @test4(<4 x i1> %a) nounwind { 48entry: 49 %q = load <4 x i1>, <4 x i1>* @Q, align 16 50 %v = and <4 x i1> %a, %q 51 ret <4 x i1> %v 52 53; CHECK-LABEL: @test4 54; CHECK-DAG: lbz 55; CHECK-DAG: qvlfdx [[REG1:[0-9]+]], 56; CHECK-DAG: stw 57; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]], 58; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]] 59; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]] 60; CHECK: qvflogical 1, 1, [[REG4]], 1 61; CHECK: blr 62} 63 64define void @test5(<4 x i1> %a) nounwind { 65entry: 66 store <4 x i1> %a, <4 x i1>* @R 67 ret void 68 69; CHECK-LABEL: @test5 70; CHECK: qvlfdx [[REG1:[0-9]+]], 71; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 72; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 73; CHECK: qvstfiwx [[REG3]], 74; CHECK: lwz 75; CHECK: stb 76; CHECK: blr 77} 78 79define i1 @test6(<4 x i1> %a) nounwind { 80entry: 81 %r = extractelement <4 x i1> %a, i32 2 82 ret i1 %r 83 84; CHECK-LABEL: @test6 85; CHECK: qvlfdx [[REG1:[0-9]+]], 86; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 87; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 88; CHECK: qvstfiwx [[REG3]], 89; CHECK: lwz 90; CHECK: blr 91} 92 93define i1 @test7(<4 x i1> %a) nounwind { 94entry: 95 %r = extractelement <4 x i1> %a, i32 2 96 %s = extractelement <4 x i1> %a, i32 3 97 %q = and i1 %r, %s 98 ret i1 %q 99 100; CHECK-LABEL: @test7 101; CHECK: qvlfdx [[REG1:[0-9]+]], 102; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 103; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 104; CHECK: qvstfiwx [[REG3]], 105; CHECK-DAG: lwz [[REG4:[0-9]+]], 106; FIXME: We're storing the vector twice, and that's silly. 107; CHECK-DAG: qvstfiwx [[REG3]], 108; CHECK: lwz [[REG5:[0-9]+]], 109; CHECK: and 3, 110; CHECK: blr 111} 112 113define i1 @test8(<3 x i1> %a) nounwind { 114entry: 115 %r = extractelement <3 x i1> %a, i32 2 116 ret i1 %r 117 118; CHECK-LABEL: @test8 119; CHECK: qvlfdx [[REG1:[0-9]+]], 120; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 121; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 122; CHECK: qvstfiwx [[REG3]], 123; CHECK: lwz 124; CHECK: blr 125} 126 127define <3 x float> @test9(<3 x float> %a, <3 x float> %b, i1 %c1, i1 %c2, i1 %c3) nounwind readnone { 128entry: 129 %v = insertelement <3 x i1> undef, i1 %c1, i32 0 130 %v2 = insertelement <3 x i1> %v, i1 %c2, i32 1 131 %v3 = insertelement <3 x i1> %v2, i1 %c3, i32 2 132 %r = select <3 x i1> %v3, <3 x float> %a, <3 x float> %b 133 ret <3 x float> %r 134 135; CHECK-LABEL: @test9 136; CHECK: stw 137; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]], 138; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], 139; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]] 140; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]] 141; CHECK: qvfsel 1, [[REG4]], 1, 2 142; CHECK: blr 143} 144 145