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1; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vperm
2
3define <4 x float> @test_uu72(<4 x float>* %P1, <4 x float>* %P2) {
4	%V1 = load <4 x float>, <4 x float>* %P1		; <<4 x float>> [#uses=1]
5	%V2 = load <4 x float>, <4 x float>* %P2		; <<4 x float>> [#uses=1]
6	%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32 2 >		; <<4 x float>> [#uses=1]
7	ret <4 x float> %V3
8}
9
10define <4 x float> @test_30u5(<4 x float>* %P1, <4 x float>* %P2) {
11	%V1 = load <4 x float>, <4 x float>* %P1		; <<4 x float>> [#uses=1]
12	%V2 = load <4 x float>, <4 x float>* %P2		; <<4 x float>> [#uses=1]
13	%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 >		; <<4 x float>> [#uses=1]
14	ret <4 x float> %V3
15}
16
17define <4 x float> @test_3u73(<4 x float>* %P1, <4 x float>* %P2) {
18	%V1 = load <4 x float>, <4 x float>* %P1		; <<4 x float>> [#uses=1]
19	%V2 = load <4 x float>, <4 x float>* %P2		; <<4 x float>> [#uses=1]
20	%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 >		; <<4 x float>> [#uses=1]
21	ret <4 x float> %V3
22}
23
24define <4 x float> @test_3774(<4 x float>* %P1, <4 x float>* %P2) {
25	%V1 = load <4 x float>, <4 x float>* %P1		; <<4 x float>> [#uses=1]
26	%V2 = load <4 x float>, <4 x float>* %P2		; <<4 x float>> [#uses=1]
27	%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 >		; <<4 x float>> [#uses=1]
28	ret <4 x float> %V3
29}
30
31define <4 x float> @test_4450(<4 x float>* %P1, <4 x float>* %P2) {
32	%V1 = load <4 x float>, <4 x float>* %P1		; <<4 x float>> [#uses=1]
33	%V2 = load <4 x float>, <4 x float>* %P2		; <<4 x float>> [#uses=1]
34	%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 >		; <<4 x float>> [#uses=1]
35	ret <4 x float> %V3
36}
37