1; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
2; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
3; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
4; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
5target datalayout = "E-m:e-i64:64-n32:64"
6target triple = "powerpc64-unknown-linux-gnu"
7
8define double @test1(double %a, double %b) {
9entry:
10  %v = fmul double %a, %b
11  ret double %v
12
13; CHECK-LABEL: @test1
14; CHECK: xsmuldp 1, 1, 2
15; CHECK: blr
16}
17
18define double @test2(double %a, double %b) {
19entry:
20  %v = fdiv double %a, %b
21  ret double %v
22
23; CHECK-LABEL: @test2
24; CHECK: xsdivdp 1, 1, 2
25; CHECK: blr
26}
27
28define double @test3(double %a, double %b) {
29entry:
30  %v = fadd double %a, %b
31  ret double %v
32
33; CHECK-LABEL: @test3
34; CHECK: xsadddp 1, 1, 2
35; CHECK: blr
36}
37
38define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
39entry:
40  %v = fadd <2 x double> %a, %b
41  ret <2 x double> %v
42
43; CHECK-LABEL: @test4
44; CHECK: xvadddp 34, 34, 35
45; CHECK: blr
46}
47
48define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
49entry:
50  %v = xor <4 x i32> %a, %b
51  ret <4 x i32> %v
52
53; CHECK-REG-LABEL: @test5
54; CHECK-REG: xxlxor 34, 34, 35
55; CHECK-REG: blr
56
57; CHECK-FISL-LABEL: @test5
58; CHECK-FISL: vor 4, 2, 2
59; CHECK-FISL: vor 5, 3, 3
60; CHECK-FISL: xxlxor 36, 36, 37
61; CHECK-FISL: vor 2, 4, 4
62; CHECK-FISL: blr
63}
64
65define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
66entry:
67  %v = xor <8 x i16> %a, %b
68  ret <8 x i16> %v
69
70; CHECK-REG-LABEL: @test6
71; CHECK-REG: xxlxor 34, 34, 35
72; CHECK-REG: blr
73
74; CHECK-FISL-LABEL: @test6
75; CHECK-FISL: vor 4, 2, 2
76; CHECK-FISL: vor 5, 3, 3
77; CHECK-FISL: xxlxor 36, 36, 37
78; CHECK-FISL: vor 2, 4, 4
79; CHECK-FISL: blr
80}
81
82define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
83entry:
84  %v = xor <16 x i8> %a, %b
85  ret <16 x i8> %v
86
87; CHECK-REG-LABEL: @test7
88; CHECK-REG: xxlxor 34, 34, 35
89; CHECK-REG: blr
90
91; CHECK-FISL-LABEL: @test7
92; CHECK-FISL: vor 4, 2, 2
93; CHECK-FISL: vor 5, 3, 3
94; CHECK-FISL: xxlxor 36, 36, 37
95; CHECK-FISL: vor 2, 4, 4
96; CHECK-FISL: blr
97}
98
99define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
100entry:
101  %v = or <4 x i32> %a, %b
102  ret <4 x i32> %v
103
104; CHECK-REG-LABEL: @test8
105; CHECK-REG: xxlor 34, 34, 35
106; CHECK-REG: blr
107
108; CHECK-FISL-LABEL: @test8
109; CHECK-FISL: vor 4, 2, 2
110; CHECK-FISL: vor 5, 3, 3
111; CHECK-FISL: xxlor 36, 36, 37
112; CHECK-FISL: vor 2, 4, 4
113; CHECK-FISL: blr
114}
115
116define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
117entry:
118  %v = or <8 x i16> %a, %b
119  ret <8 x i16> %v
120
121; CHECK-REG-LABEL: @test9
122; CHECK-REG: xxlor 34, 34, 35
123; CHECK-REG: blr
124
125; CHECK-FISL-LABEL: @test9
126; CHECK-FISL: vor 4, 2, 2
127; CHECK-FISL: vor 5, 3, 3
128; CHECK-FISL: xxlor 36, 36, 37
129; CHECK-FISL: vor 2, 4, 4
130; CHECK-FISL: blr
131}
132
133define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
134entry:
135  %v = or <16 x i8> %a, %b
136  ret <16 x i8> %v
137
138; CHECK-REG-LABEL: @test10
139; CHECK-REG: xxlor 34, 34, 35
140; CHECK-REG: blr
141
142; CHECK-FISL-LABEL: @test10
143; CHECK-FISL: vor 4, 2, 2
144; CHECK-FISL: vor 5, 3, 3
145; CHECK-FISL: xxlor 36, 36, 37
146; CHECK-FISL: vor 2, 4, 4
147; CHECK-FISL: blr
148}
149
150define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
151entry:
152  %v = and <4 x i32> %a, %b
153  ret <4 x i32> %v
154
155; CHECK-REG-LABEL: @test11
156; CHECK-REG: xxland 34, 34, 35
157; CHECK-REG: blr
158
159; CHECK-FISL-LABEL: @test11
160; CHECK-FISL: vor 4, 2, 2
161; CHECK-FISL: vor 5, 3, 3
162; CHECK-FISL: xxland 36, 36, 37
163; CHECK-FISL: vor 2, 4, 4
164; CHECK-FISL: blr
165}
166
167define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
168entry:
169  %v = and <8 x i16> %a, %b
170  ret <8 x i16> %v
171
172; CHECK-REG-LABEL: @test12
173; CHECK-REG: xxland 34, 34, 35
174; CHECK-REG: blr
175
176; CHECK-FISL-LABEL: @test12
177; CHECK-FISL: vor 4, 2, 2
178; CHECK-FISL: vor 5, 3, 3
179; CHECK-FISL: xxland 36, 36, 37
180; CHECK-FISL: vor 2, 4, 4
181; CHECK-FISL: blr
182}
183
184define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
185entry:
186  %v = and <16 x i8> %a, %b
187  ret <16 x i8> %v
188
189; CHECK-REG-LABEL: @test13
190; CHECK-REG: xxland 34, 34, 35
191; CHECK-REG: blr
192
193; CHECK-FISL-LABEL: @test13
194; CHECK-FISL: vor 4, 2, 2
195; CHECK-FISL: vor 5, 3, 3
196; CHECK-FISL: xxland 36, 36, 37
197; CHECK-FISL: vor 2, 4, 4
198; CHECK-FISL: blr
199}
200
201define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
202entry:
203  %v = or <4 x i32> %a, %b
204  %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>
205  ret <4 x i32> %w
206
207; CHECK-REG-LABEL: @test14
208; CHECK-REG: xxlnor 34, 34, 35
209; CHECK-REG: blr
210
211; CHECK-FISL-LABEL: @test14
212; CHECK-FISL: vor 4, 2, 2
213; CHECK-FISL: vor 5, 3, 3
214; CHECK-FISL: xxlor 36, 36, 37
215; CHECK-FISL: vor 0, 4, 4
216; CHECK-FISL: vor 4, 2, 2
217; CHECK-FISL: vor 5, 3, 3
218; CHECK-FISL: xxlnor 36, 36, 37
219; CHECK-FISL: vor 2, 4, 4
220; CHECK-FISL: lis 0, -1
221; CHECK-FISL: ori 0, 0, 65520
222; CHECK-FISL: stvx 0, 1, 0
223; CHECK-FISL: blr
224}
225
226define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
227entry:
228  %v = or <8 x i16> %a, %b
229  %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
230  ret <8 x i16> %w
231
232; CHECK-REG-LABEL: @test15
233; CHECK-REG: xxlnor 34, 34, 35
234; CHECK-REG: blr
235
236; CHECK-FISL-LABEL: @test15
237; CHECK-FISL: vor 4, 2, 2
238; CHECK-FISL: vor 5, 3, 3
239; CHECK-FISL: xxlor 36, 36, 37
240; CHECK-FISL: vor 0, 4, 4
241; CHECK-FISL: vor 4, 2, 2
242; CHECK-FISL: vor 5, 3, 3
243; CHECK-FISL: xxlnor 36, 36, 37
244; CHECK-FISL: vor 2, 4, 4
245; CHECK-FISL: lis 0, -1
246; CHECK-FISL: ori 0, 0, 65520
247; CHECK-FISL: stvx 0, 1, 0
248; CHECK-FISL: blr
249}
250
251define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
252entry:
253  %v = or <16 x i8> %a, %b
254  %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
255  ret <16 x i8> %w
256
257; CHECK-REG-LABEL: @test16
258; CHECK-REG: xxlnor 34, 34, 35
259; CHECK-REG: blr
260
261; CHECK-FISL-LABEL: @test16
262; CHECK-FISL: vor 4, 2, 2
263; CHECK-FISL: vor 5, 3, 3
264; CHECK-FISL: xxlor 36, 36, 37
265; CHECK-FISL: vor 0, 4, 4
266; CHECK-FISL: vor 4, 2, 2
267; CHECK-FISL: vor 5, 3, 3
268; CHECK-FISL: xxlnor 36, 36, 37
269; CHECK-FISL: vor 2, 4, 4
270; CHECK-FISL: lis 0, -1
271; CHECK-FISL: ori 0, 0, 65520
272; CHECK-FISL: stvx 0, 1, 0
273; CHECK-FISL: blr
274}
275
276define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
277entry:
278  %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
279  %v = and <4 x i32> %a, %w
280  ret <4 x i32> %v
281
282; CHECK-REG-LABEL: @test17
283; CHECK-REG: xxlandc 34, 34, 35
284; CHECK-REG: blr
285
286; CHECK-FISL-LABEL: @test17
287; CHECK-FISL: vspltisb 4, -1
288; CHECK-FISL: vor 5, 3, 3
289; CHECK-FISL: vor 0, 4, 4
290; CHECK-FISL: xxlxor 37, 37, 32
291; CHECK-FISL: vor 3, 5, 5
292; CHECK-FISL: vor 5, 2, 2
293; CHECK-FISL: vor 0, 3, 3
294; CHECK-FISL: xxland 37, 37, 32
295; CHECK-FISL: vor 2, 5, 5
296; CHECK-FISL: blr
297}
298
299define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
300entry:
301  %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
302  %v = and <8 x i16> %a, %w
303  ret <8 x i16> %v
304
305; CHECK-REG-LABEL: @test18
306; CHECK-REG: xxlandc 34, 34, 35
307; CHECK-REG: blr
308
309; CHECK-FISL-LABEL: @test18
310; CHECK-FISL: vspltisb 4, -1
311; CHECK-FISL: vor 5, 3, 3
312; CHECK-FISL: vor 0, 4, 4
313; CHECK-FISL: xxlxor 37, 37, 32
314; CHECK-FISL: vor 4, 5, 5
315; CHECK-FISL: vor 5, 2, 2
316; CHECK-FISL: vor 0, 3, 3
317; CHECK-FISL: xxlandc 37, 37, 32
318; CHECK-FISL: vor 2, 5, 5
319; CHECK-FISL: lis 0, -1
320; CHECK-FISL: ori 0, 0, 65520
321; CHECK-FISL: stvx 4, 1, 0
322; CHECK-FISL: blr
323}
324
325define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
326entry:
327  %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
328  %v = and <16 x i8> %a, %w
329  ret <16 x i8> %v
330
331; CHECK-REG-LABEL: @test19
332; CHECK-REG: xxlandc 34, 34, 35
333; CHECK-REG: blr
334
335; CHECK-FISL-LABEL: @test19
336; CHECK-FISL: vspltisb 4, -1
337; CHECK-FISL: vor 5, 3, 3
338; CHECK-FISL: vor 0, 4, 4
339; CHECK-FISL: xxlxor 37, 37, 32
340; CHECK-FISL: vor 4, 5, 5
341; CHECK-FISL: vor 5, 2, 2
342; CHECK-FISL: vor 0, 3, 3
343; CHECK-FISL: xxlandc 37, 37, 32
344; CHECK-FISL: vor 2, 5, 5
345; CHECK-FISL: lis 0, -1
346; CHECK-FISL: ori 0, 0, 65520
347; CHECK-FISL: stvx 4, 1, 0
348; CHECK-FISL: blr
349}
350
351define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
352entry:
353  %m = icmp eq <4 x i32> %c, %d
354  %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
355  ret <4 x i32> %v
356
357; CHECK-REG-LABEL: @test20
358; CHECK-REG: vcmpequw {{[0-9]+}}, 4, 5
359; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
360; CHECK-REG: blr
361
362; CHECK-FISL-LABEL: @test20
363; CHECK-FISL: vcmpequw 4, 4, 5
364; CHECK-FISL: vor 0, 3, 3
365; CHECK-FISL: vor 1, 2, 2
366; CHECK-FISL: vor 6, 4, 4
367; CHECK-FISL: xxsel 32, 32, 33, 38
368; CHECK-FISL: vor 2, 0, 0
369; CHECK-FISL: blr
370}
371
372define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
373entry:
374  %m = fcmp oeq <4 x float> %c, %d
375  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
376  ret <4 x float> %v
377
378; CHECK-REG-LABEL: @test21
379; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37
380; CHECK-REG: xxsel 34, 35, 34, [[V1]]
381; CHECK-REG: blr
382
383; CHECK-FISL-LABEL: @test21
384; CHECK-FISL: vor 0, 5, 5
385; CHECK-FISL: vor 1, 4, 4
386; CHECK-FISL: vor 6, 3, 3
387; CHECK-FISL: vor 7, 2, 2
388; CHECK-FISL: xvcmpeqsp 32, 33, 32
389; CHECK-FISL: xxsel 32, 38, 39, 32
390; CHECK-FISL: vor 2, 0, 0
391; CHECK-FISL: blr
392}
393
394define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
395entry:
396  %m = fcmp ueq <4 x float> %c, %d
397  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
398  ret <4 x float> %v
399
400; CHECK-REG-LABEL: @test22
401; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
402; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
403; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
404; CHECK-REG-DAG: xxlnor
405; CHECK-REG-DAG: xxlnor
406; CHECK-REG-DAG: xxlor
407; CHECK-REG-DAG: xxlor
408; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
409; CHECK-REG: blr
410
411; CHECK-FISL-LABEL: @test22
412; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 32
413; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 32, 32
414; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 33
415; CHECK-FISL-DAG: xxlnor
416; CHECK-FISL-DAG: xxlnor
417; CHECK-FISL-DAG: xxlor
418; CHECK-FISL-DAG: xxlor
419; CHECK-FISL: xxsel 0, 38, 39, {{[0-9]+}}
420; CHECK-FISL: blr
421}
422
423define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
424entry:
425  %m = icmp eq <8 x i16> %c, %d
426  %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
427  ret <8 x i16> %v
428
429; CHECK-REG-LABEL: @test23
430; CHECK-REG: vcmpequh {{[0-9]+}}, 4, 5
431; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
432; CHECK-REG: blr
433
434; CHECK-FISL-LABEL: @test23
435; CHECK-FISL: vcmpequh 4, 4, 5
436; CHECK-FISL: vor 0, 3, 3
437; CHECK-FISL: vor 1, 2, 2
438; CHECK-FISL: vor 6, 4, 4
439; CHECK-FISL: xxsel 32, 32, 33, 38
440; CHECK-FISL: vor 2, 0,
441; CHECK-FISL: blr
442}
443
444define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
445entry:
446  %m = icmp eq <16 x i8> %c, %d
447  %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
448  ret <16 x i8> %v
449
450; CHECK-REG-LABEL: @test24
451; CHECK-REG: vcmpequb {{[0-9]+}}, 4, 5
452; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
453; CHECK-REG: blr
454
455; CHECK-FISL-LABEL: @test24
456; CHECK-FISL: vcmpequb 4, 4, 5
457; CHECK-FISL: vor 0, 3, 3
458; CHECK-FISL: vor 1, 2, 2
459; CHECK-FISL: vor 6, 4, 4
460; CHECK-FISL: xxsel 32, 32, 33, 38
461; CHECK-FISL: vor 2, 0, 0
462; CHECK-FISL: blr
463}
464
465define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
466entry:
467  %m = fcmp oeq <2 x double> %c, %d
468  %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
469  ret <2 x double> %v
470
471; CHECK-LABEL: @test25
472; CHECK: xvcmpeqdp [[V1:[0-9]+]], 36, 37
473; CHECK: xxsel 34, 35, 34, [[V1]]
474; CHECK: blr
475}
476
477define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
478  %v = add <2 x i64> %a, %b
479  ret <2 x i64> %v
480
481; CHECK-LABEL: @test26
482
483; Make sure we use only two stores (one for each operand).
484; CHECK: stxvd2x 35,
485; CHECK: stxvd2x 34,
486; CHECK-NOT: stxvd2x
487
488; FIXME: The code quality here is not good; just make sure we do something for now.
489; CHECK: add
490; CHECK: add
491; CHECK: blr
492}
493
494define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
495  %v = and <2 x i64> %a, %b
496  ret <2 x i64> %v
497
498; CHECK-LABEL: @test27
499; CHECK: xxland 34, 34, 35
500; CHECK: blr
501}
502
503define <2 x double> @test28(<2 x double>* %a) {
504  %v = load <2 x double>, <2 x double>* %a, align 16
505  ret <2 x double> %v
506
507; CHECK-LABEL: @test28
508; CHECK: lxvd2x 34, 0, 3
509; CHECK: blr
510}
511
512define void @test29(<2 x double>* %a, <2 x double> %b) {
513  store <2 x double> %b, <2 x double>* %a, align 16
514  ret void
515
516; CHECK-LABEL: @test29
517; CHECK: stxvd2x 34, 0, 3
518; CHECK: blr
519}
520
521define <2 x double> @test28u(<2 x double>* %a) {
522  %v = load <2 x double>, <2 x double>* %a, align 8
523  ret <2 x double> %v
524
525; CHECK-LABEL: @test28u
526; CHECK: lxvd2x 34, 0, 3
527; CHECK: blr
528}
529
530define void @test29u(<2 x double>* %a, <2 x double> %b) {
531  store <2 x double> %b, <2 x double>* %a, align 8
532  ret void
533
534; CHECK-LABEL: @test29u
535; CHECK: stxvd2x 34, 0, 3
536; CHECK: blr
537}
538
539define <2 x i64> @test30(<2 x i64>* %a) {
540  %v = load <2 x i64>, <2 x i64>* %a, align 16
541  ret <2 x i64> %v
542
543; CHECK-REG-LABEL: @test30
544; CHECK-REG: lxvd2x 34, 0, 3
545; CHECK-REG: blr
546
547; CHECK-FISL-LABEL: @test30
548; CHECK-FISL: lxvd2x 0, 0, 3
549; CHECK-FISL: xxlor 34, 0, 0
550; CHECK-FISL: vor 3, 2, 2
551; CHECK-FISL: vor 2, 3, 3
552; CHECK-FISL: blr
553}
554
555define void @test31(<2 x i64>* %a, <2 x i64> %b) {
556  store <2 x i64> %b, <2 x i64>* %a, align 16
557  ret void
558
559; CHECK-LABEL: @test31
560; CHECK: stxvd2x 34, 0, 3
561; CHECK: blr
562}
563
564define <4 x float> @test32(<4 x float>* %a) {
565  %v = load <4 x float>, <4 x float>* %a, align 16
566  ret <4 x float> %v
567
568; CHECK-REG-LABEL: @test32
569; CHECK-REG: lxvw4x 34, 0, 3
570; CHECK-REG: blr
571
572; CHECK-FISL-LABEL: @test32
573; CHECK-FISL: lxvw4x 0, 0, 3
574; CHECK-FISL: xxlor 34, 0, 0
575; CHECK-FISL: blr
576}
577
578define void @test33(<4 x float>* %a, <4 x float> %b) {
579  store <4 x float> %b, <4 x float>* %a, align 16
580  ret void
581
582; CHECK-REG-LABEL: @test33
583; CHECK-REG: stxvw4x 34, 0, 3
584; CHECK-REG: blr
585
586; CHECK-FISL-LABEL: @test33
587; CHECK-FISL: vor 3, 2, 2
588; CHECK-FISL: stxvw4x 35, 0, 3
589; CHECK-FISL: blr
590}
591
592define <4 x float> @test32u(<4 x float>* %a) {
593  %v = load <4 x float>, <4 x float>* %a, align 8
594  ret <4 x float> %v
595
596; CHECK-LABEL: @test32u
597; CHECK-DAG: lvsl
598; CHECK-DAG: lvx
599; CHECK-DAG: lvx
600; CHECK: vperm 2,
601; CHECK: blr
602}
603
604define void @test33u(<4 x float>* %a, <4 x float> %b) {
605  store <4 x float> %b, <4 x float>* %a, align 8
606  ret void
607
608; CHECK-REG-LABEL: @test33u
609; CHECK-REG: stxvw4x 34, 0, 3
610; CHECK-REG: blr
611
612; CHECK-FISL-LABEL: @test33u
613; CHECK-FISL: vor 3, 2, 2
614; CHECK-FISL: stxvw4x 35, 0, 3
615; CHECK-FISL: blr
616}
617
618define <4 x i32> @test34(<4 x i32>* %a) {
619  %v = load <4 x i32>, <4 x i32>* %a, align 16
620  ret <4 x i32> %v
621
622; CHECK-REG-LABEL: @test34
623; CHECK-REG: lxvw4x 34, 0, 3
624; CHECK-REG: blr
625
626; CHECK-FISL-LABEL: @test34
627; CHECK-FISL: lxvw4x 0, 0, 3
628; CHECK-FISL: xxlor 34, 0, 0
629; CHECK-FISL: vor 3, 2, 2
630; CHECK-FISL: vor 2, 3, 3
631; CHECK-FISL: blr
632}
633
634define void @test35(<4 x i32>* %a, <4 x i32> %b) {
635  store <4 x i32> %b, <4 x i32>* %a, align 16
636  ret void
637
638; CHECK-REG-LABEL: @test35
639; CHECK-REG: stxvw4x 34, 0, 3
640; CHECK-REG: blr
641
642; CHECK-FISL-LABEL: @test35
643; CHECK-FISL: vor 3, 2, 2
644; CHECK-FISL: stxvw4x 35, 0, 3
645; CHECK-FISL: blr
646}
647
648define <2 x double> @test40(<2 x i64> %a) {
649  %v = uitofp <2 x i64> %a to <2 x double>
650  ret <2 x double> %v
651
652; CHECK-LABEL: @test40
653; CHECK: xvcvuxddp 34, 34
654; CHECK: blr
655}
656
657define <2 x double> @test41(<2 x i64> %a) {
658  %v = sitofp <2 x i64> %a to <2 x double>
659  ret <2 x double> %v
660
661; CHECK-LABEL: @test41
662; CHECK: xvcvsxddp 34, 34
663; CHECK: blr
664}
665
666define <2 x i64> @test42(<2 x double> %a) {
667  %v = fptoui <2 x double> %a to <2 x i64>
668  ret <2 x i64> %v
669
670; CHECK-LABEL: @test42
671; CHECK: xvcvdpuxds 34, 34
672; CHECK: blr
673}
674
675define <2 x i64> @test43(<2 x double> %a) {
676  %v = fptosi <2 x double> %a to <2 x i64>
677  ret <2 x i64> %v
678
679; CHECK-LABEL: @test43
680; CHECK: xvcvdpsxds 34, 34
681; CHECK: blr
682}
683
684define <2 x float> @test44(<2 x i64> %a) {
685  %v = uitofp <2 x i64> %a to <2 x float>
686  ret <2 x float> %v
687
688; CHECK-LABEL: @test44
689; FIXME: The code quality here looks pretty bad.
690; CHECK: blr
691}
692
693define <2 x float> @test45(<2 x i64> %a) {
694  %v = sitofp <2 x i64> %a to <2 x float>
695  ret <2 x float> %v
696
697; CHECK-LABEL: @test45
698; FIXME: The code quality here looks pretty bad.
699; CHECK: blr
700}
701
702define <2 x i64> @test46(<2 x float> %a) {
703  %v = fptoui <2 x float> %a to <2 x i64>
704  ret <2 x i64> %v
705
706; CHECK-LABEL: @test46
707; FIXME: The code quality here looks pretty bad.
708; CHECK: blr
709}
710
711define <2 x i64> @test47(<2 x float> %a) {
712  %v = fptosi <2 x float> %a to <2 x i64>
713  ret <2 x i64> %v
714
715; CHECK-LABEL: @test47
716; FIXME: The code quality here looks pretty bad.
717; CHECK: blr
718}
719
720define <2 x double> @test50(double* %a) {
721  %v = load double, double* %a, align 8
722  %w = insertelement <2 x double> undef, double %v, i32 0
723  %x = insertelement <2 x double> %w, double %v, i32 1
724  ret <2 x double> %x
725
726; CHECK-LABEL: @test50
727; CHECK: lxvdsx 34, 0, 3
728; CHECK: blr
729}
730
731define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
732  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0>
733  ret <2 x double> %v
734
735; CHECK-LABEL: @test51
736; CHECK: xxpermdi 34, 34, 34, 0
737; CHECK: blr
738}
739
740define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
741  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>
742  ret <2 x double> %v
743
744; CHECK-LABEL: @test52
745; CHECK: xxpermdi 34, 34, 35, 0
746; CHECK: blr
747}
748
749define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
750  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0>
751  ret <2 x double> %v
752
753; CHECK-LABEL: @test53
754; CHECK: xxpermdi 34, 35, 34, 0
755; CHECK: blr
756}
757
758define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
759  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
760  ret <2 x double> %v
761
762; CHECK-LABEL: @test54
763; CHECK: xxpermdi 34, 34, 35, 2
764; CHECK: blr
765}
766
767define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
768  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>
769  ret <2 x double> %v
770
771; CHECK-LABEL: @test55
772; CHECK: xxpermdi 34, 34, 35, 3
773; CHECK: blr
774}
775
776define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
777  %v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
778  ret <2 x i64> %v
779
780; CHECK-LABEL: @test56
781; CHECK: xxpermdi 34, 34, 35, 3
782; CHECK: blr
783}
784
785define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
786  %v = shl <2 x i64> %a, %b
787  ret <2 x i64> %v
788
789; CHECK-LABEL: @test60
790; This should scalarize, and the current code quality is not good.
791; CHECK: stxvd2x
792; CHECK: stxvd2x
793; CHECK: sld
794; CHECK: sld
795; CHECK: lxvd2x
796; CHECK: blr
797}
798
799define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
800  %v = lshr <2 x i64> %a, %b
801  ret <2 x i64> %v
802
803; CHECK-LABEL: @test61
804; This should scalarize, and the current code quality is not good.
805; CHECK: stxvd2x
806; CHECK: stxvd2x
807; CHECK: srd
808; CHECK: srd
809; CHECK: lxvd2x
810; CHECK: blr
811}
812
813define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
814  %v = ashr <2 x i64> %a, %b
815  ret <2 x i64> %v
816
817; CHECK-LABEL: @test62
818; This should scalarize, and the current code quality is not good.
819; CHECK: stxvd2x
820; CHECK: stxvd2x
821; CHECK: srad
822; CHECK: srad
823; CHECK: lxvd2x
824; CHECK: blr
825}
826
827define double @test63(<2 x double> %a) {
828  %v = extractelement <2 x double> %a, i32 0
829  ret double %v
830
831; CHECK-REG-LABEL: @test63
832; CHECK-REG: xxlor 1, 34, 34
833; CHECK-REG: blr
834
835; CHECK-FISL-LABEL: @test63
836; CHECK-FISL: xxlor 0, 34, 34
837; CHECK-FISL: fmr 1, 0
838; CHECK-FISL: blr
839}
840
841define double @test64(<2 x double> %a) {
842  %v = extractelement <2 x double> %a, i32 1
843  ret double %v
844
845; CHECK-REG-LABEL: @test64
846; CHECK-REG: xxpermdi 1, 34, 34, 2
847; CHECK-REG: blr
848
849; CHECK-FISL-LABEL: @test64
850; CHECK-FISL: xxpermdi 34, 34, 34, 2
851; CHECK-FISL: xxlor 0, 34, 34
852; CHECK-FISL: fmr 1, 0
853; CHECK-FISL: blr
854}
855
856define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
857  %w = icmp eq <2 x i64> %a, %b
858  ret <2 x i1> %w
859
860; CHECK-REG-LABEL: @test65
861; CHECK-REG: vcmpequw 2, 2, 3
862; CHECK-REG: blr
863
864; CHECK-FISL-LABEL: @test65
865; CHECK-FISL: vor 4, 3, 3
866; CHECK-FISL: vor 5, 2, 2
867; CHECK-FISL: vcmpequw 4, 5, 4
868; CHECK-FISL: vor 2, 4, 4
869; CHECK-FISL: blr
870}
871
872define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
873  %w = icmp ne <2 x i64> %a, %b
874  ret <2 x i1> %w
875
876; CHECK-REG-LABEL: @test66
877; CHECK-REG: vcmpequw {{[0-9]+}}, 2, 3
878; CHECK-REG: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
879; CHECK-REG: blr
880
881; CHECK-FISL-LABEL: @test66
882; CHECK-FISL: vcmpequw {{[0-9]+}}, 5, 4
883; CHECK-FISL: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
884; CHECK-FISL: blr
885}
886
887define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
888  %w = icmp ult <2 x i64> %a, %b
889  ret <2 x i1> %w
890
891; CHECK-LABEL: @test67
892; This should scalarize, and the current code quality is not good.
893; CHECK: stxvd2x
894; CHECK: stxvd2x
895; CHECK: cmpld
896; CHECK: cmpld
897; CHECK: lxvd2x
898; CHECK: blr
899}
900
901define <2 x double> @test68(<2 x i32> %a) {
902  %w = sitofp <2 x i32> %a to <2 x double>
903  ret <2 x double> %w
904
905; CHECK-LABEL: @test68
906; CHECK: xxsldwi [[V1:[0-9]+]], 34, 34, 1
907; CHECK: xvcvsxwdp 34, [[V1]]
908; CHECK: blr
909}
910
911define <2 x double> @test69(<2 x i16> %a) {
912  %w = sitofp <2 x i16> %a to <2 x double>
913  ret <2 x double> %w
914
915; CHECK-LABEL: @test69
916; CHECK: vspltisw [[V1:[0-9]+]], 8
917; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
918; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
919; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]]
920; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
921; CHECK: xvcvsxwdp 34, [[V4]]
922; CHECK: blr
923}
924
925define <2 x double> @test70(<2 x i8> %a) {
926  %w = sitofp <2 x i8> %a to <2 x double>
927  ret <2 x double> %w
928
929; CHECK-LABEL: @test70
930; CHECK: vspltisw [[V1:[0-9]+]], 12
931; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
932; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
933; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]]
934; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
935; CHECK: xvcvsxwdp 34, [[V4]]
936; CHECK: blr
937}
938
939define <2 x i32> @test80(i32 %v) {
940  %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
941  %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
942  %i = add <2 x i32> %b2, <i32 2, i32 3>
943  ret <2 x i32> %i
944
945; CHECK-REG-LABEL: @test80
946; CHECK-REG-DAG: addi [[R1:[0-9]+]], 3, 3
947; CHECK-REG-DAG: addi [[R2:[0-9]+]], 1, -16
948; CHECK-REG-DAG: addi [[R3:[0-9]+]], 3, 2
949; CHECK-REG: std [[R1]], -8(1)
950; CHECK-REG: std [[R3]], -16(1)
951; CHECK-REG: lxvd2x 34, 0, [[R2]]
952; CHECK-REG-NOT: stxvd2x
953; CHECK-REG: blr
954
955; CHECK-FISL-LABEL: @test80
956; CHECK-FISL-DAG: addi [[R1:[0-9]+]], 3, 3
957; CHECK-FISL-DAG: addi [[R2:[0-9]+]], 1, -16
958; CHECK-FISL-DAG: addi [[R3:[0-9]+]], 3, 2
959; CHECK-FISL-DAG: std [[R1]], -8(1)
960; CHECK-FISL-DAG: std [[R3]], -16(1)
961; CHECK-FISL-DAG: lxvd2x 0, 0, [[R2]]
962; CHECK-FISL: blr
963}
964
965define <2 x double> @test81(<4 x float> %b) {
966  %w = bitcast <4 x float> %b to <2 x double>
967  ret <2 x double> %w
968
969; CHECK-LABEL: @test81
970; CHECK: blr
971}
972
973define double @test82(double %a, double %b, double %c, double %d) {
974entry:
975  %m = fcmp oeq double %c, %d
976  %v = select i1 %m, double %a, double %b
977  ret double %v
978
979; CHECK-REG-LABEL: @test82
980; CHECK-REG: xscmpudp [[REG:[0-9]+]], 3, 4
981; CHECK-REG: beqlr [[REG]]
982
983; CHECK-FISL-LABEL: @test82
984; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4
985; CHECK-FISL: beq [[REG]], {{.*}}
986}
987