1; RUN: llc < %s -mtriple=sparc64-pc-openbsd -disable-sparc-leaf-proc | FileCheck %s
2; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9.
3
4; CHECK: cmpri
5; CHECK: cmp %i1, 1
6; CHECK: be %xcc,
7define void @cmpri(i64* %p, i64 %x) {
8entry:
9  %tobool = icmp eq i64 %x, 1
10  br i1 %tobool, label %if.end, label %if.then
11
12if.then:
13  store i64 %x, i64* %p, align 8
14  br label %if.end
15
16if.end:
17  ret void
18}
19
20; CHECK: cmprr
21; CHECK: cmp %i1, %i2
22; CHECK: bgu %xcc,
23define void @cmprr(i64* %p, i64 %x, i64 %y) {
24entry:
25  %tobool = icmp ugt i64 %x, %y
26  br i1 %tobool, label %if.end, label %if.then
27
28if.then:
29  store i64 %x, i64* %p, align 8
30  br label %if.end
31
32if.end:
33  ret void
34}
35
36; CHECK: selecti32_xcc
37; CHECK: cmp %i0, %i1
38; CHECK: movg %xcc, %i2, %i3
39; CHECK: restore %g0, %i3, %o0
40define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) {
41entry:
42  %tobool = icmp sgt i64 %x, %y
43  %rv = select i1 %tobool, i32 %a, i32 %b
44  ret i32 %rv
45}
46
47; CHECK: selecti64_xcc
48; CHECK: cmp %i0, %i1
49; CHECK: movg %xcc, %i2, %i3
50; CHECK: restore %g0, %i3, %o0
51define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) {
52entry:
53  %tobool = icmp sgt i64 %x, %y
54  %rv = select i1 %tobool, i64 %a, i64 %b
55  ret i64 %rv
56}
57
58; CHECK: selecti64_icc
59; CHECK: cmp %i0, %i1
60; CHECK: movg %icc, %i2, %i3
61; CHECK: restore %g0, %i3, %o0
62define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) {
63entry:
64  %tobool = icmp sgt i32 %x, %y
65  %rv = select i1 %tobool, i64 %a, i64 %b
66  ret i64 %rv
67}
68
69; CHECK: selecti64_fcc
70; CHECK: fcmps %f1, %f3
71; CHECK: movul %fcc0, %i2, %i3
72; CHECK: restore %g0, %i3, %o0
73define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) {
74entry:
75  %tobool = fcmp ult float %x, %y
76  %rv = select i1 %tobool, i64 %a, i64 %b
77  ret i64 %rv
78}
79
80; CHECK: selectf32_xcc
81; CHECK: cmp %i0, %i1
82; CHECK: fmovsg %xcc, %f5, %f7
83; CHECK: fmovs %f7, %f0
84define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
85entry:
86  %tobool = icmp sgt i64 %x, %y
87  %rv = select i1 %tobool, float %a, float %b
88  ret float %rv
89}
90
91; CHECK: selectf64_xcc
92; CHECK: cmp %i0, %i1
93; CHECK: fmovdg %xcc, %f4, %f6
94; CHECK: fmovd %f6, %f0
95define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
96entry:
97  %tobool = icmp sgt i64 %x, %y
98  %rv = select i1 %tobool, double %a, double %b
99  ret double %rv
100}
101
102; The MOVXCC instruction can't use %g0 for its tied operand.
103; CHECK: select_consti64_xcc
104; CHECK: cmp
105; CHECK: movg %xcc, 123, %i{{[0-2]}}
106define i64 @select_consti64_xcc(i64 %x, i64 %y) {
107entry:
108  %tobool = icmp sgt i64 %x, %y
109  %rv = select i1 %tobool, i64 123, i64 0
110  ret i64 %rv
111}
112
113; CHECK-LABEL: setcc_resultty
114; CHECK-DAG:       srax %i0, 63, %o0
115; CHECK-DAG:       mov %i0, %o1
116; CHECK-DAG:       mov 0, %o2
117; CHECK-DAG:       mov 32, %o3
118; CHECK-DAG:       call __multi3
119; CHECK:       cmp
120; CHECK:       movne %xcc, 1, [[R:%[gilo][0-7]]]
121; CHECK:       or [[R]], %i1, %i0
122
123define i1 @setcc_resultty(i64 %a, i1 %b) {
124  %a0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 32)
125  %a1 = extractvalue { i64, i1 } %a0, 1
126  %a4 = or i1 %a1, %b
127  ret i1 %a4
128}
129
130declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
131