1; REQUIRES: asserts
2; RUN: llc -march=x86 -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness
3; RUN: llc -march=x86-64 -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness
4
5; PR6497
6
7; Chain and flag folding issues.
8define i32 @test1() nounwind ssp {
9entry:
10  %tmp5.i = load volatile i32, i32* undef              ; <i32> [#uses=1]
11  %conv.i = zext i32 %tmp5.i to i64               ; <i64> [#uses=1]
12  %tmp12.i = load volatile i32, i32* undef             ; <i32> [#uses=1]
13  %conv13.i = zext i32 %tmp12.i to i64            ; <i64> [#uses=1]
14  %shl.i = shl i64 %conv13.i, 32                  ; <i64> [#uses=1]
15  %or.i = or i64 %shl.i, %conv.i                  ; <i64> [#uses=1]
16  %add16.i = add i64 %or.i, 256                   ; <i64> [#uses=1]
17  %shr.i = lshr i64 %add16.i, 8                   ; <i64> [#uses=1]
18  %conv19.i = trunc i64 %shr.i to i32             ; <i32> [#uses=1]
19  store volatile i32 %conv19.i, i32* undef
20  ret i32 undef
21}
22
23; PR6533
24define void @test2(i1 %x, i32 %y) nounwind {
25  %land.ext = zext i1 %x to i32                   ; <i32> [#uses=1]
26  %and = and i32 %y, 1                        ; <i32> [#uses=1]
27  %xor = xor i32 %and, %land.ext                  ; <i32> [#uses=1]
28  %cmp = icmp eq i32 %xor, 1                      ; <i1> [#uses=1]
29  br i1 %cmp, label %if.end, label %if.then
30
31if.then:                                          ; preds = %land.end
32  ret void
33
34if.end:                                           ; preds = %land.end
35  ret void
36}
37
38; PR6577
39%pair = type { i64, double }
40
41define void @test3() {
42dependentGraph243.exit:
43  %subject19 = load %pair, %pair* undef                     ; <%1> [#uses=1]
44  %0 = extractvalue %pair %subject19, 1              ; <double> [#uses=2]
45  %1 = select i1 undef, double %0, double undef   ; <double> [#uses=1]
46  %2 = select i1 undef, double %1, double %0      ; <double> [#uses=1]
47  %3 = insertvalue %pair undef, double %2, 1         ; <%1> [#uses=1]
48  store %pair %3, %pair* undef
49  ret void
50}
51
52; PR6605
53define i64 @test4(i8* %P) nounwind ssp {
54entry:
55  %tmp1 = load i8, i8* %P                           ; <i8> [#uses=3]
56  %tobool = icmp eq i8 %tmp1, 0                   ; <i1> [#uses=1]
57  %tmp58 = sext i1 %tobool to i8                  ; <i8> [#uses=1]
58  %mul.i = and i8 %tmp58, %tmp1                   ; <i8> [#uses=1]
59  %conv6 = zext i8 %mul.i to i32                  ; <i32> [#uses=1]
60  %cmp = icmp ne i8 %tmp1, 1                      ; <i1> [#uses=1]
61  %conv11 = zext i1 %cmp to i32                   ; <i32> [#uses=1]
62  %call12 = tail call i32 @safe(i32 %conv11) nounwind ; <i32> [#uses=1]
63  %and = and i32 %conv6, %call12                  ; <i32> [#uses=1]
64  %tobool13 = icmp eq i32 %and, 0                 ; <i1> [#uses=1]
65  br i1 %tobool13, label %if.else, label %return
66
67if.else:                                          ; preds = %entry
68  br label %return
69
70return:                                           ; preds = %if.else, %entry
71  ret i64 undef
72}
73
74declare i32 @safe(i32)
75
76; PR6607
77define fastcc void @test5(i32 %FUNC) nounwind {
78foo:
79  %0 = load i8, i8* undef, align 1                    ; <i8> [#uses=3]
80  %1 = sext i8 %0 to i32                          ; <i32> [#uses=2]
81  %2 = zext i8 %0 to i32                          ; <i32> [#uses=1]
82  %tmp1.i5037 = urem i32 %2, 10                   ; <i32> [#uses=1]
83  %tmp.i5038 = icmp ugt i32 %tmp1.i5037, 15       ; <i1> [#uses=1]
84  %3 = zext i1 %tmp.i5038 to i8                   ; <i8> [#uses=1]
85  %4 = icmp slt i8 %0, %3                         ; <i1> [#uses=1]
86  %5 = add nsw i32 %1, 256                        ; <i32> [#uses=1]
87  %storemerge.i.i57 = select i1 %4, i32 %5, i32 %1 ; <i32> [#uses=1]
88  %6 = shl i32 %storemerge.i.i57, 16              ; <i32> [#uses=1]
89  %7 = sdiv i32 %6, -256                          ; <i32> [#uses=1]
90  %8 = trunc i32 %7 to i8                         ; <i8> [#uses=1]
91  store i8 %8, i8* undef, align 1
92  ret void
93}
94
95
96; Crash commoning identical asms.
97; PR6803
98define void @test6(i1 %C) nounwind optsize ssp {
99entry:
100  br i1 %C, label %do.body55, label %do.body92
101
102do.body55:                                        ; preds = %if.else36
103  call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !0
104  ret void
105
106do.body92:                                        ; preds = %if.then66
107  call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !1
108  ret void
109}
110
111!0 = !{i32 633550}
112!1 = !{i32 634261}
113
114
115; Crash during XOR optimization.
116; <rdar://problem/7869290>
117
118define void @test7() nounwind ssp {
119entry:
120  br i1 undef, label %bb14, label %bb67
121
122bb14:
123  %tmp0 = trunc i16 undef to i1
124  %tmp1 = load i8, i8* undef, align 8
125  %tmp2 = shl i8 %tmp1, 4
126  %tmp3 = lshr i8 %tmp2, 7
127  %tmp4 = trunc i8 %tmp3 to i1
128  %tmp5 = icmp ne i1 %tmp0, %tmp4
129  br i1 %tmp5, label %bb14, label %bb67
130
131bb67:
132  ret void
133}
134
135; Crash when trying to copy AH to AL.
136; PR7540
137define void @copy8bitregs() nounwind {
138entry:
139  %div.i = sdiv i32 115200, 0
140  %shr8.i = lshr i32 %div.i, 8
141  %conv4.i = trunc i32 %shr8.i to i8
142  call void asm sideeffect "outb $0, ${1:w}", "{ax},N{dx},~{dirflag},~{fpsr},~{flags}"(i8 %conv4.i, i32 1017) nounwind
143  unreachable
144}
145
146; Crash trying to form conditional increment with fp value.
147; PR8981
148define i32 @test9(double %X) ssp align 2 {
149entry:
150  %0 = fcmp one double %X, 0.000000e+00
151  %cond = select i1 %0, i32 1, i32 2
152  ret i32 %cond
153}
154
155
156; PR8514 - Crash in match address do to "heroics" turning and-of-shift into
157; shift of and.
158%struct.S0 = type { i8, [2 x i8], i8 }
159
160define void @func_59(i32 %p_63) noreturn nounwind {
161entry:
162  br label %for.body
163
164for.body:                                         ; preds = %for.inc44, %entry
165  %p_63.addr.1 = phi i32 [ %p_63, %entry ], [ 0, %for.inc44 ]
166  %l_74.0 = phi i32 [ 0, %entry ], [ %add46, %for.inc44 ]
167  br i1 undef, label %for.inc44, label %bb.nph81
168
169bb.nph81:                                         ; preds = %for.body
170  %tmp98 = add i32 %p_63.addr.1, 0
171  br label %for.body22
172
173for.body22:                                       ; preds = %for.body22, %bb.nph81
174  %l_75.077 = phi i64 [ %ins, %for.body22 ], [ undef, %bb.nph81 ]
175  %tmp110 = trunc i64 %l_75.077 to i32
176  %tmp111 = and i32 %tmp110, 65535
177  %arrayidx32.0 = getelementptr [9 x [5 x [2 x %struct.S0]]], [9 x [5 x [2 x %struct.S0]]]* undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 %tmp111, i32 0
178  store i8 1, i8* %arrayidx32.0, align 4
179  %tmp106 = shl i32 %tmp110, 2
180  %tmp107 = and i32 %tmp106, 262140
181  %scevgep99.sum114 = or i32 %tmp107, 1
182  %arrayidx32.1.1 = getelementptr [9 x [5 x [2 x %struct.S0]]], [9 x [5 x [2 x %struct.S0]]]* undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 0, i32 1, i32 %scevgep99.sum114
183  store i8 0, i8* %arrayidx32.1.1, align 1
184  %ins = or i64 undef, undef
185  br label %for.body22
186
187for.inc44:                                        ; preds = %for.body
188  %add46 = add i32 %l_74.0, 1
189  br label %for.body
190}
191
192; PR9028
193define void @func_60(i64 %A) nounwind {
194entry:
195  %0 = zext i64 %A to i160
196  %1 = shl i160 %0, 64
197  %2 = zext i160 %1 to i576
198  %3 = zext i96 undef to i576
199  %4 = or i576 %3, %2
200  store i576 %4, i576* undef, align 8
201  ret void
202}
203
204; <rdar://problem/9187792>
205define fastcc void @func_61() nounwind sspreq {
206entry:
207  %t1 = tail call i64 @llvm.objectsize.i64.p0i8(i8* undef, i1 false)
208  %t2 = icmp eq i64 %t1, -1
209  br i1 %t2, label %bb2, label %bb1
210
211bb1:
212  ret void
213
214bb2:
215  ret void
216}
217
218declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) nounwind readnone
219
220; PR10277
221; This test has dead code elimination caused by remat during spilling.
222; DCE causes a live interval to break into connected components.
223; One of the components is spilled.
224
225%t2 = type { i8 }
226%t9 = type { %t10 }
227%t10 = type { %t11 }
228%t11 = type { %t12 }
229%t12 = type { %t13*, %t13*, %t13* }
230%t13 = type { %t14*, %t15, %t15 }
231%t14 = type opaque
232%t15 = type { i8, i32, i32 }
233%t16 = type { %t17, i8* }
234%t17 = type { %t18 }
235%t18 = type { %t19 }
236%t19 = type { %t20*, %t20*, %t20* }
237%t20 = type { i32, i32 }
238%t21 = type { %t13* }
239
240define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 {
241bb:
242  %tmp = load %t9*, %t9** undef, align 4
243  %tmp2 = getelementptr inbounds %t9, %t9* %tmp, i32 0, i32 0
244  %tmp3 = getelementptr inbounds %t9, %t9* %tmp, i32 0, i32 0, i32 0, i32 0, i32 1
245  br label %bb4
246
247bb4:                                              ; preds = %bb37, %bb
248  %tmp5 = phi i96 [ undef, %bb ], [ %tmp38, %bb37 ]
249  %tmp6 = phi i96 [ undef, %bb ], [ %tmp39, %bb37 ]
250  br i1 undef, label %bb34, label %bb7
251
252bb7:                                              ; preds = %bb4
253  %tmp8 = load i32, i32* undef, align 4
254  %tmp9 = and i96 %tmp6, 4294967040
255  %tmp10 = zext i32 %tmp8 to i96
256  %tmp11 = shl nuw nsw i96 %tmp10, 32
257  %tmp12 = or i96 %tmp9, %tmp11
258  %tmp13 = or i96 %tmp12, 1
259  %tmp14 = load i32, i32* undef, align 4
260  %tmp15 = and i96 %tmp5, 4294967040
261  %tmp16 = zext i32 %tmp14 to i96
262  %tmp17 = shl nuw nsw i96 %tmp16, 32
263  %tmp18 = or i96 %tmp15, %tmp17
264  %tmp19 = or i96 %tmp18, 1
265  %tmp20 = load i8, i8* undef, align 1
266  %tmp21 = and i8 %tmp20, 1
267  %tmp22 = icmp ne i8 %tmp21, 0
268  %tmp23 = select i1 %tmp22, i96 %tmp19, i96 %tmp13
269  %tmp24 = select i1 %tmp22, i96 %tmp13, i96 %tmp19
270  store i96 %tmp24, i96* undef, align 4
271  %tmp25 = load %t13*, %t13** %tmp3, align 4
272  %tmp26 = icmp eq %t13* %tmp25, undef
273  br i1 %tmp26, label %bb28, label %bb27
274
275bb27:                                             ; preds = %bb7
276  br label %bb29
277
278bb28:                                             ; preds = %bb7
279  call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef)
280  br label %bb29
281
282bb29:                                             ; preds = %bb28, %bb27
283  store i96 %tmp23, i96* undef, align 4
284  %tmp30 = load %t13*, %t13** %tmp3, align 4
285  br i1 false, label %bb33, label %bb31
286
287bb31:                                             ; preds = %bb29
288  %tmp32 = getelementptr inbounds %t13, %t13* %tmp30, i32 1
289  store %t13* %tmp32, %t13** %tmp3, align 4
290  br label %bb37
291
292bb33:                                             ; preds = %bb29
293  unreachable
294
295bb34:                                             ; preds = %bb4
296  br i1 undef, label %bb36, label %bb35
297
298bb35:                                             ; preds = %bb34
299  store %t13* null, %t13** %tmp3, align 4
300  br label %bb37
301
302bb36:                                             ; preds = %bb34
303  call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef)
304  br label %bb37
305
306bb37:                                             ; preds = %bb36, %bb35, %bb31
307  %tmp38 = phi i96 [ %tmp23, %bb31 ], [ %tmp5, %bb35 ], [ %tmp5, %bb36 ]
308  %tmp39 = phi i96 [ %tmp24, %bb31 ], [ %tmp6, %bb35 ], [ %tmp6, %bb36 ]
309  %tmp40 = add i32 undef, 1
310  br label %bb4
311}
312
313declare %t14* @_ZN4llvm9MCContext16CreateTempSymbolEv(%t2*)
314
315declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10*, %t21* byval align 4, %t13*)
316
317declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
318
319declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
320
321; PR10463
322; Spilling a virtual register with <undef> uses.
323define void @autogen_239_1000() {
324BB:
325    %Shuff = shufflevector <8 x double> undef, <8 x double> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 undef>
326    br label %CF
327
328CF:
329    %B16 = frem <8 x double> zeroinitializer, %Shuff
330    %E19 = extractelement <8 x double> %Shuff, i32 5
331    br i1 undef, label %CF, label %CF75
332
333CF75:
334    br i1 undef, label %CF75, label %CF76
335
336CF76:
337    store double %E19, double* undef
338    br i1 undef, label %CF76, label %CF77
339
340CF77:
341    %B55 = fmul <8 x double> %B16, undef
342    br label %CF77
343}
344
345; PR10527
346define void @pr10527() nounwind uwtable {
347entry:
348  br label %"4"
349
350"3":
351  %0 = load <2 x i32>, <2 x i32>* null, align 8
352  %1 = xor <2 x i32> zeroinitializer, %0
353  %2 = and <2 x i32> %1, %6
354  %3 = or <2 x i32> undef, %2
355  %4 = and <2 x i32> %3, undef
356  store <2 x i32> %4, <2 x i32>* undef
357  %5 = load <2 x i32>, <2 x i32>* undef, align 1
358  br label %"4"
359
360"4":
361  %6 = phi <2 x i32> [ %5, %"3" ], [ zeroinitializer, %entry ]
362  %7 = icmp ult i32 undef, undef
363  br i1 %7, label %"3", label %"5"
364
365"5":
366  ret void
367}
368
369; PR11078
370;
371; A virtual register used by the "foo" inline asm memory operand gets
372; constrained to GR32_ABCD during coalescing.  This makes the inline asm
373; impossible to allocate without splitting the live range and reinflating the
374; register class around the inline asm.
375;
376; The constraint originally comes from the TEST8ri optimization of (icmp (and %t0, 1), 0).
377
378@__force_order = external hidden global i32, align 4
379define void @pr11078(i32* %pgd) nounwind {
380entry:
381  %t0 = load i32, i32* %pgd, align 4
382  %and2 = and i32 %t0, 1
383  %tobool = icmp eq i32 %and2, 0
384  br i1 %tobool, label %if.then, label %if.end
385
386if.then:
387  %t1 = tail call i32 asm sideeffect "bar", "=r,=*m,~{dirflag},~{fpsr},~{flags}"(i32* @__force_order) nounwind
388  br label %if.end
389
390if.end:
391  %t6 = inttoptr i32 %t0 to i64*
392  %t11 = tail call i64 asm sideeffect "foo", "=*m,=A,{bx},{cx},1,~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %t6, i32 0, i32 0, i64 0) nounwind
393  ret void
394}
395
396; Avoid emitting wrong kill flags from InstrEmitter.
397; InstrEmitter::EmitSubregNode() may steal virtual registers from already
398; emitted blocks when isCoalescableExtInstr points out the opportunity.
399; Make sure kill flags are cleared on the newly global virtual register.
400define i64 @ov_read(i8* %vf, i8* nocapture %buffer, i32 %length, i32 %bigendianp, i32 %word, i32 %sgned, i32* %bitstream) nounwind uwtable ssp {
401entry:
402  br i1 undef, label %return, label %while.body.preheader
403
404while.body.preheader:                             ; preds = %entry
405  br i1 undef, label %if.then3, label %if.end7
406
407if.then3:                                         ; preds = %while.body.preheader
408  %0 = load i32, i32* undef, align 4
409  br i1 undef, label %land.lhs.true.i255, label %if.end7
410
411land.lhs.true.i255:                               ; preds = %if.then3
412  br i1 undef, label %if.then.i256, label %if.end7
413
414if.then.i256:                                     ; preds = %land.lhs.true.i255
415  %sub.i = sub i32 0, %0
416  %conv = sext i32 %sub.i to i64
417  br i1 undef, label %if.end7, label %while.end
418
419if.end7:                                          ; preds = %if.then.i256, %land.lhs.true.i255, %if.then3, %while.body.preheader
420  unreachable
421
422while.end:                                        ; preds = %if.then.i256
423  %cmp18 = icmp sgt i32 %sub.i, 0
424  %.conv = select i1 %cmp18, i64 -131, i64 %conv
425  ret i64 %.conv
426
427return:                                           ; preds = %entry
428  ret i64 -131
429}
430
431; The tail call to a varargs function sets %AL.
432; uitofp expands to an FCMOV instruction which splits the basic block.
433; Make sure the live range of %AL isn't split.
434@.str = private unnamed_addr constant { [1 x i8], [63 x i8] } zeroinitializer, align 32
435define void @pr13188(i64* nocapture %this) uwtable ssp sanitize_address align 2 {
436entry:
437  %x7 = load i64, i64* %this, align 8
438  %sub = add i64 %x7, -1
439  %conv = uitofp i64 %sub to float
440  %div = fmul float %conv, 5.000000e-01
441  %conv2 = fpext float %div to double
442  tail call void (...) @_Z6PrintFz(i8* getelementptr inbounds ({ [1 x i8], [63 x i8] }, { [1 x i8], [63 x i8] }* @.str, i64 0, i32 0, i64 0), double %conv2)
443  ret void
444}
445declare void @_Z6PrintFz(...)
446
447@a = external global i32, align 4
448@fn1.g = private unnamed_addr constant [9 x i32*] [i32* null, i32* @a, i32* null, i32* null, i32* null, i32* null, i32* null, i32* null, i32* null], align 16
449@e = external global i32, align 4
450
451define void @pr13943() nounwind uwtable ssp {
452entry:
453  %srcval = load i576, i576* bitcast ([9 x i32*]* @fn1.g to i576*), align 16
454  br label %for.cond
455
456for.cond:                                         ; preds = %for.inc, %entry
457  %g.0 = phi i576 [ %srcval, %entry ], [ %ins, %for.inc ]
458  %0 = load i32, i32* @e, align 4
459  %1 = lshr i576 %g.0, 64
460  %2 = trunc i576 %1 to i64
461  %3 = inttoptr i64 %2 to i32*
462  %cmp = icmp eq i32* undef, %3
463  %conv2 = zext i1 %cmp to i32
464  %and = and i32 %conv2, %0
465  tail call void (...) @fn3(i32 %and) nounwind
466  %tobool = icmp eq i32 undef, 0
467  br i1 %tobool, label %for.inc, label %if.then
468
469if.then:                                          ; preds = %for.cond
470  ret void
471
472for.inc:                                          ; preds = %for.cond
473  %4 = shl i576 %1, 384
474  %mask = and i576 %g.0, -726838724295606890509921801691610055141362320587174446476410459910173841445449629921945328942266354949348255351381262292727973638307841
475  %5 = and i576 %4, 726838724295606890509921801691610055141362320587174446476410459910173841445449629921945328942266354949348255351381262292727973638307840
476  %ins = or i576 %5, %mask
477  br label %for.cond
478}
479
480declare void @fn3(...)
481
482; Check coalescing of IMPLICIT_DEF instructions:
483;
484; %vreg1 = IMPLICIT_DEF
485; %vreg2 = MOV32r0
486;
487; When coalescing %vreg1 and %vreg2, the IMPLICIT_DEF instruction should be
488; erased along with its value number.
489;
490define void @rdar12474033() nounwind ssp {
491bb:
492  br i1 undef, label %bb21, label %bb1
493
494bb1:                                              ; preds = %bb
495  switch i32 undef, label %bb10 [
496    i32 4, label %bb2
497    i32 1, label %bb9
498    i32 5, label %bb3
499    i32 6, label %bb3
500    i32 2, label %bb9
501  ]
502
503bb2:                                              ; preds = %bb1
504  unreachable
505
506bb3:                                              ; preds = %bb1, %bb1
507  br i1 undef, label %bb4, label %bb5
508
509bb4:                                              ; preds = %bb3
510  unreachable
511
512bb5:                                              ; preds = %bb3
513  %tmp = load <4 x float>, <4 x float>* undef, align 1
514  %tmp6 = bitcast <4 x float> %tmp to i128
515  %tmp7 = load <4 x float>, <4 x float>* undef, align 1
516  %tmp8 = bitcast <4 x float> %tmp7 to i128
517  br label %bb10
518
519bb9:                                              ; preds = %bb1, %bb1
520  unreachable
521
522bb10:                                             ; preds = %bb5, %bb1
523  %tmp11 = phi i128 [ undef, %bb1 ], [ %tmp6, %bb5 ]
524  %tmp12 = phi i128 [ 0, %bb1 ], [ %tmp8, %bb5 ]
525  switch i32 undef, label %bb21 [
526    i32 2, label %bb18
527    i32 3, label %bb13
528    i32 5, label %bb16
529    i32 6, label %bb17
530    i32 1, label %bb18
531  ]
532
533bb13:                                             ; preds = %bb10
534  br i1 undef, label %bb15, label %bb14
535
536bb14:                                             ; preds = %bb13
537  br label %bb21
538
539bb15:                                             ; preds = %bb13
540  unreachable
541
542bb16:                                             ; preds = %bb10
543  unreachable
544
545bb17:                                             ; preds = %bb10
546  unreachable
547
548bb18:                                             ; preds = %bb10, %bb10
549  %tmp19 = bitcast i128 %tmp11 to <4 x float>
550  %tmp20 = bitcast i128 %tmp12 to <4 x float>
551  br label %bb21
552
553bb21:                                             ; preds = %bb18, %bb14, %bb10, %bb
554  %tmp22 = phi <4 x float> [ undef, %bb ], [ undef, %bb10 ], [ undef, %bb14 ], [ %tmp20, %bb18 ]
555  %tmp23 = phi <4 x float> [ undef, %bb ], [ undef, %bb10 ], [ undef, %bb14 ], [ %tmp19, %bb18 ]
556  store <4 x float> %tmp23, <4 x float>* undef, align 16
557  store <4 x float> %tmp22, <4 x float>* undef, align 16
558  switch i32 undef, label %bb29 [
559    i32 5, label %bb27
560    i32 1, label %bb24
561    i32 2, label %bb25
562    i32 14, label %bb28
563    i32 4, label %bb26
564  ]
565
566bb24:                                             ; preds = %bb21
567  unreachable
568
569bb25:                                             ; preds = %bb21
570  br label %bb29
571
572bb26:                                             ; preds = %bb21
573  br label %bb29
574
575bb27:                                             ; preds = %bb21
576  unreachable
577
578bb28:                                             ; preds = %bb21
579  br label %bb29
580
581bb29:                                             ; preds = %bb28, %bb26, %bb25, %bb21
582  unreachable
583}
584
585define void @pr14194() nounwind uwtable {
586  %tmp = load i64, i64* undef, align 16
587  %tmp1 = trunc i64 %tmp to i32
588  %tmp2 = lshr i64 %tmp, 32
589  %tmp3 = trunc i64 %tmp2 to i32
590  %tmp4 = call { i32, i32 } asm sideeffect "", "=&r,=&r,r,r,0,1,~{dirflag},~{fpsr},~{flags}"(i32 %tmp3, i32 undef, i32 %tmp3, i32 %tmp1) nounwind
591 ret void
592}
593