1; RUN: llc < %s -march=x86-64 -mcpu=core2 | FileCheck %s -check-prefix=SSE -check-prefix=CHECK
2; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s -check-prefix=AVX -check-prefix=CHECK
3
4; Test ADDSUB ISel patterns.
5
6; Functions below are obtained from the following source:
7;
8; typedef double double2 __attribute__((ext_vector_type(2)));
9; typedef double double4 __attribute__((ext_vector_type(4)));
10; typedef float float4 __attribute__((ext_vector_type(4)));
11; typedef float float8 __attribute__((ext_vector_type(8)));
12;
13; float4 test1(float4 A, float4 B) {
14;   float4 X = A - B;
15;   float4 Y = A + B;
16;   return (float4){X[0], Y[1], X[2], Y[3]};
17; }
18;
19; float8 test2(float8 A, float8 B) {
20;   float8 X = A - B;
21;   float8 Y = A + B;
22;   return (float8){X[0], Y[1], X[2], Y[3], X[4], Y[5], X[6], Y[7]};
23; }
24;
25; double4 test3(double4 A, double4 B) {
26;   double4 X = A - B;
27;   double4 Y = A + B;
28;   return (double4){X[0], Y[1], X[2], Y[3]};
29; }
30;
31; double2 test4(double2 A, double2 B) {
32;   double2 X = A - B;
33;   double2 Y = A + B;
34;   return (double2){X[0], Y[1]};
35; }
36
37define <4 x float> @test1(<4 x float> %A, <4 x float> %B) {
38  %sub = fsub <4 x float> %A, %B
39  %add = fadd <4 x float> %A, %B
40  %vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
41  ret <4 x float> %vecinit6
42}
43; CHECK-LABEL: test1
44; SSE: addsubps
45; AVX: vaddsubps
46; CHECK-NEXT: ret
47
48
49define <8 x float> @test2(<8 x float> %A, <8 x float> %B) {
50  %sub = fsub <8 x float> %A, %B
51  %add = fadd <8 x float> %A, %B
52  %vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
53  ret <8 x float> %vecinit14
54}
55; CHECK-LABEL: test2
56; SSE: addsubps
57; SSE-NEXT: addsubps
58; AVX: vaddsubps
59; AVX-NOT: vaddsubps
60; CHECK: ret
61
62
63define <4 x double> @test3(<4 x double> %A, <4 x double> %B) {
64  %sub = fsub <4 x double> %A, %B
65  %add = fadd <4 x double> %A, %B
66  %vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
67  ret <4 x double> %vecinit6
68}
69; CHECK-LABEL: test3
70; SSE: addsubpd
71; SSE: addsubpd
72; AVX: vaddsubpd
73; AVX-NOT: vaddsubpd
74; CHECK: ret
75
76
77define <2 x double> @test4(<2 x double> %A, <2 x double> %B) #0 {
78  %add = fadd <2 x double> %A, %B
79  %sub = fsub <2 x double> %A, %B
80  %vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
81  ret <2 x double> %vecinit2
82}
83; CHECK-LABEL: test4
84; SSE: addsubpd
85; AVX: vaddsubpd
86; CHECK-NEXT: ret
87
88
89define <4 x float> @test1b(<4 x float> %A, <4 x float>* %B) {
90  %1 = load <4 x float>, <4 x float>* %B
91  %add = fadd <4 x float> %A, %1
92  %sub = fsub <4 x float> %A, %1
93  %vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
94  ret <4 x float> %vecinit6
95}
96; CHECK-LABEL: test1b
97; SSE: addsubps
98; AVX: vaddsubps
99; CHECK-NEXT: ret
100
101
102define <8 x float> @test2b(<8 x float> %A, <8 x float>* %B) {
103  %1 = load <8 x float>, <8 x float>* %B
104  %add = fadd <8 x float> %A, %1
105  %sub = fsub <8 x float> %A, %1
106  %vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
107  ret <8 x float> %vecinit14
108}
109; CHECK-LABEL: test2b
110; SSE: addsubps
111; SSE-NEXT: addsubps
112; AVX: vaddsubps
113; AVX-NOT: vaddsubps
114; CHECK: ret
115
116
117define <4 x double> @test3b(<4 x double> %A, <4 x double>* %B) {
118  %1 = load <4 x double>, <4 x double>* %B
119  %add = fadd <4 x double> %A, %1
120  %sub = fsub <4 x double> %A, %1
121  %vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
122  ret <4 x double> %vecinit6
123}
124; CHECK-LABEL: test3b
125; SSE: addsubpd
126; SSE: addsubpd
127; AVX: vaddsubpd
128; AVX-NOT: vaddsubpd
129; CHECK: ret
130
131
132define <2 x double> @test4b(<2 x double> %A, <2 x double>* %B) {
133  %1 = load <2 x double>, <2 x double>* %B
134  %sub = fsub <2 x double> %A, %1
135  %add = fadd <2 x double> %A, %1
136  %vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
137  ret <2 x double> %vecinit2
138}
139; CHECK-LABEL: test4b
140; SSE: addsubpd
141; AVX: vaddsubpd
142; CHECK-NEXT: ret
143
144