Lines Matching refs:IntRegs
531 ``FPRegs``, ``DFPRegs``, and ``IntRegs``. For all three register classes, the
546 def IntRegs : RegisterClass<"SP", [i32], 32,
573 associated register classes. The order of registers in ``IntRegs`` reflects
574 the order in the definition of ``IntRegs`` in the target description file.
578 // IntRegs Register Class...
579 static const unsigned IntRegs[] = {
598 // IntRegs Sub-register Classess...
603 // IntRegs Super-register Classess...
608 // IntRegs Register Class sub-classes...
613 // IntRegs Register Class super-classes...
620 IntRegsSuperRegClasses, 4, 4, 1, IntRegs, IntRegs + 32) {}
763 target description file (``IntRegs``).
767 def LDrr : F3_1 <3, 0b000000, (outs IntRegs:$dst), (ins MEMrr:$addr),
778 let MIOperandInfo = (ops IntRegs, IntRegs);
795 def LDri : F3_2 <3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr),
810 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
814 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
863 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
1229 def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
1293 // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)