Lines Matching refs:SPARC

23 ARM, and SPARC.  The backend may also be used to generate code targeted at SPUs
29 assembly) for a SPARC target, because SPARC has fairly standard
63 To follow the SPARC examples in this document, have a copy of `The SPARC
181 SPARC target, name the files ``SparcTargetMachine.h`` and
192 For instance, for the SPARC target, the header file ``SparcTargetMachine.h``
425 In ``SparcRegisterInfo.td``, additional register classes are defined for SPARC:
427 and ``Rd``.  SPARC registers are identified by 5-bit ID numbers, which is a
563 be included in the header file for the implementation of the SPARC register
571 included at the bottom of ``SparcRegisterInfo.cpp``, the SPARC register
635 for the SPARC implementation in ``SparcRegisterInfo.cpp``:
725 of the target machine (such as the SPARC Architecture Manual for the SPARC
741 As is described in the SPARC Architecture Manual, Version 8, there are three
753 ``Pseudo`` for synthetic SPARC instructions.
756 for the SPARC target.  In ``SparcInstrInfo.td``, the following target
758 Word (the ``LD`` SPARC opcode) from a memory address to a register.  The first
830 ``SparcInstrInfo.td`` indicate the bit location of the SPARC condition code.
846 (Note that ``Sparc.h`` also defines enums that correspond to the same SPARC
1037 Here's a list of functions that are overridden for the SPARC implementation in
1075 examined as models for your own ``AnalyzeBranch`` implementation.  Since SPARC
1354 may be promoted to a larger type that is supported.  For example, SPARC does
1368 of other operations may be used to similar effect.  In SPARC, the
1427 SPARC v9.  The following code enables the ``Expand`` conversion technique for
1428 non-v9 SPARC implementations.
1664 set variations for a given chip set.  For example, the LLVM SPARC
1665 implementation provided covers three major versions of the SPARC microprocessor
1704                        "Enable SPARC-V9 instructions">;
1712 define particular SPARC processor subtypes that may have the previously