Lines Matching refs:Dm
284 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
285 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
286 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
300 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
301 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
302 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
316 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
317 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
318 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
328 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
329 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
330 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
343 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
344 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
345 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
366 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
367 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
368 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
388 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
389 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
390 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
408 (outs), (ins DPR:$Dd, DPR:$Dm),
409 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
410 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
423 (outs), (ins DPR:$Dd, DPR:$Dm),
424 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
442 (outs DPR:$Dd), (ins DPR:$Dm),
443 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
444 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
516 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
517 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
518 [(set SPR:$Sd, (fround DPR:$Dm))]> {
521 bits<5> Dm;
524 let Inst{3-0} = Dm{3-0};
525 let Inst{5} = Dm{4};
574 (outs SPR:$Sd), (ins DPR:$Dm),
575 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
579 bits<5> Dm;
582 let Inst{3-0} = Dm{3-0};
583 let Inst{5} = Dm{4};
601 (outs SPR:$Sd), (ins DPR:$Dm),
602 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
606 bits<5> Dm;
611 let Inst{3-0} = Dm{3-0};
612 let Inst{5} = Dm{4};
647 (outs SPR:$Sd), (ins DPR:$Dm),
648 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
651 bits<5> Dm;
656 let Inst{3-0} = Dm{3-0};
657 let Inst{5} = Dm{4};
662 (outs SPR:$Sd), (ins DPR:$Dm),
663 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
666 bits<5> Dm;
671 let Inst{3-0} = Dm{3-0};
672 let Inst{5} = Dm{4};
705 (outs DPR:$Dd), (ins DPR:$Dm),
706 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
707 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
728 (outs DPR:$Dd), (ins DPR:$Dm),
729 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
730 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
739 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
740 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
759 (outs DPR:$Dd), (ins DPR:$Dm),
760 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
761 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
770 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
771 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>,
781 (outs DPR:$Dd), (ins DPR:$Dm),
782 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
783 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
792 (outs DPR:$Dd), (ins DPR:$Dm),
793 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
850 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
851 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
854 bits<5> Dm;
859 let Inst{3-0} = Dm{3-0};
860 let Inst{5} = Dm{4};
871 // $Rt = EXTRACT_SUBREG $Dm, ssub_0
872 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
903 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
904 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
905 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
907 bits<5> Dm;
912 let Inst{3-0} = Dm{3-0};
913 let Inst{5} = Dm{4};
924 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1
1088 bits<5> Dm;
1091 let Inst{3-0} = Dm{3-0};
1092 let Inst{5} = Dm{4};
1118 (outs SPR:$Sd), (ins DPR:$Dm),
1119 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1151 (outs SPR:$Sd), (ins DPR:$Dm),
1152 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1187 (outs SPR:$Sd), (ins DPR:$Dm),
1188 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1189 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1201 (outs SPR:$Sd), (ins DPR:$Dm),
1202 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1203 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1357 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1358 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1359 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1384 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1385 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1386 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1411 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1412 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1413 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1438 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1439 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1440 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1467 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1468 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1469 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1494 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1495 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1502 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1503 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1504 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1529 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1530 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1536 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1537 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1544 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1545 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1546 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1571 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1572 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1578 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1579 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1586 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1587 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1588 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1613 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1614 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1620 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1621 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1627 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1628 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1639 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
1642 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
1840 def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",
1841 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1844 def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1845 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1849 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;